Abstract: High-level synthesis implementation of data structures in hardware can include detecting, within a design and using computer hardware, a data structure and a compiler directive for the data structure. The design may be specified in a high-level programming language. Using the computer hardware and based on the compiler directive, a modified version of the design may be created by, at least in part, generating a modified version of the data structure based on the compiler directive. Using the computer hardware, a circuit design may be generated from the modified version of the design by creating, at least in part, a hardware memory architecture for the circuit design and mapping the modified version of the data structure onto the hardware memory architecture.

Abstract: Disclosed approaches monitor states of a plurality of sets of a plurality of handshake signals. Each set of handshake signals is associated with a respective one sub-circuit of a plurality of sub-circuits. For each sub-circuit, a beginning of an iteration by the sub-circuit is detected based on states of the plurality of handshake signals of the set associated with the sub-circuit. A graphics object is generated in response to detecting the beginning of the iteration. The graphics object is displayed on a display device and overlaid on a timeline associated with the sub-circuit. The graphics object has a bound that corresponds to the beginning of the iteration. The end of the iteration is detected based on the states of the associated set of handshake signals, and the graphics object is bounded on the timeline to indicate the end of the iteration.

Abstract: A method of storing data includes the steps of storing data comprising the steps of identifying respective lifetimes of each member of an indexed collection of data elements, each of the data elements referenceable in a data index space representing a set of valid data element indices; identifying a set of pairs of the data elements having overlapping lifetimes; and generating a mapping from the data index space to an address offset space based on the set of pairs of the data elements having the overlapping lifetimes.

Abstract: A method of storing data includes the steps of storing data comprising the steps of identifying respective lifetimes of each member of an indexed collection of data elements, each of the data elements referenceable in a data index space representing a set of valid data element indices; identifying a set of pairs of the data elements having overlapping lifetimes; and generating a mapping from the data index space to an address offset space based on the set of pairs of the data elements having the overlapping lifetimes.

Abstract: A parallel compiler maps iterations of a nested loop to processor elements in a parallel array and schedules a start time for each iteration such that the processor elements are fully utilized without being overloaded. The compiler employs an efficient and direct method for generating a set of iteration schedules that satisfy the following constraints: no more than one iteration is in initiated per processor element in a specified initiation interval, and a new iteration begins on each processor element nearly every initiation interval. Since the iteration scheduling method efficiently generates a set of schedules, the compiler can select an iteration schedule that is optimized based on other criteria, such as memory bandwidth, local memory size of each processor element, estimated hardware cost of each processor element, etc.

Abstract: A parallel compiler exploits temporal recursion to reduce the cost of control code generated in transforming a sequential nested loop program into a set of parallel processes mapped to an array of processors. A parallel compiler process transforms a nested loop program into a set of single loops, where each single loop is assigned to execute on a processor element in a parallel processor array. The parallel compiler obtains a mapping of iterations of the nested loop to processor elements in the array and a schedule of start times for initiating execution of the iterations on corresponding processor elements in the array. Based on this mapping and iteration schedule, the parallel compiler generates code to compute iteration coordinates on a processor element for an iteration of the single loop from iteration coordinates computed on the same processor element for a previous iteration of the single loop.