Abstract: The invention relates to a power factor control circuit (10) and to a universal mains power supply (100). The power factor control circuit comprises input nodes (n1, n2) which receive a rectified input voltage being a rectified mains input voltage, and a drive circuit (IC1) which drives a switch (M1). A series arrangement of the switch and an inductor (L1) is arranged between the input nodes. A series arrangement of a rectifier (D1) and an output capacitor (C2) is arranged parallel to the inductor (L1). The rectifier is non-conductive when the switch is closed. The drive circuit drives the switch for generating a substantially sinusoidal current through the switch being substantially synchronized with a sinusoidal voltage of the mains input voltage. Due to the arrangement the output capacitor in the power factor control circuit according to the invention, the output capacitor can only be charged after a first conducting cycle of the switch.

Abstract: A drive circuit (DR) drives a plurality of LED strings (DS1, DS2; DS10) each comprising at least one LED (Di). The drive circuit comprises a resonance inductor (K1), and a plurality of branches which each comprise a series arrangement of a resonance capacitor (C31, C32; C34, C35) and an associated one of the plurality of LED strings (DS1, DS2; DS10). The resonance capacitor (C31, C32; C34, C35) is arranged between the resonance inductor (K1) and its associated one of the plurality of LED strings (DS1, DS2; DS10) to receive a resonance voltage (VAC) from the resonance inductor (K1). A level and frequency of the resonance voltage (VAC) and an impedance of the resonance capacitor (C31, C32; C34, C35) are selected to obtain a current source supplying a LED current (IL1 IL2; IL10) through the associated one of the plurality of LED strings (DS1, DS2; DS10) which is substantially independent on a tolerance on forward voltages of LED's of the associated one of the plurality of LED strings (DS1, DS2; DS10).

Abstract: The invention relates to a power factor control circuit (10) and to a universal mains power supply (100). The power factor control circuit comprises input nodes (n1, n2) which receive a rectified input voltage being a rectified mains input voltage, and a drive circuit (IC1) which drives a switch (M1). A series arrangement of the switch and an inductor (L1) is arranged between the input nodes. A series arrangement of a rectifier (D1) and an output capacitor (C2) is arranged parallel to the inductor (L1). The rectifier is non-conductive when the switch is closed. The drive circuit drives the switch for generating a substantially sinusoidal current through the switch being substantially synchronized with a sinusoidal voltage of the mains input voltage. Due to the arrangement the output capacitor in the power factor control circuit according to the invention, the output capacitor can only be charged after a first conducting cycle of the switch.

Abstract: The display apparatus (10) includes a signal processor (20), an illumination source (40) and a pixel array (50) for optically modulating the light generated by the illumination source (40) to generate a series of images for user-viewing. The illumination source (40) comprises a plurality of individually addressable segments (s1 to sn; s1,1 to sp,q) for generating light and having mutually independently controllable light emissions. The signal processor (20) processes and input signal (vi) to drive the illumination source (40) and the pixel array (50) so as to display the series of images corresponding to the input signal (vi). The segments (s1 to sn; s1,1 to sp,q) of the illumination source (40) are excited in operation by the signal processor (20) in response to a degree of motion occurring in corresponding parts of the input signal (vi).

Abstract: A picture display apparatus includes a non-synchronized self-oscillating switched-mode power supply (SMPS) associated with a line output stage (35) which generates power supply voltages for other elements of the apparatus, the standby state being obtained by stopping the line scan. The switch (1) of the SMPS is a MOS-type field effect transistor, and it is turned on by a winding (6) which is magnetically coupled to a ballast inductance (5), this winding (6) having one end connected to the connection point (50) between the switch and the ballast inductance, and generates, at its other end (51), a control voltage which is in phase opposition with the voltage generated in the ballast inductance, the control voltage being transmitted to the gate of the field-effect transistor (1). A capacitor (42) is arranged as a shunt across the drain-source path of the FET and creates an oscillating circuit together with the ballast inductance (5).

Abstract: In a line deflection circuit including an "S"0 correction capacitor in series with the deflection winding a second "S" capacitor is inserted in series with the first one, and there is impressed a sawtooth current at line frequency whose amplitude varies at field frequency by an auxiliary circuit similar to the main deflection circuit and of a source whose voltage varies parabolically with the field frequency. The supply circuit applies a d.c. voltage substantially without field modulation to the series arrangement formed by the two S capacitors.

Abstract: Television receiver including a switched-mode power supply which is regulated and capable of functioning both in self-oscillating mode and under the control of a line frequency synchronization. During normal operation there is synchronization, and the line time base supplies most of the supply voltages to the circuits of the receiver. To change to the stand-by state the drive of the line transistor is stopped, which stops most of the circuits depending thereon. The switched-mode power supply continues to function but then in the self-oscillating mode, and supplies the stand-by device via a secondary winding of its storage inductor.

Abstract: Method and device by which, at a given instant, a conductor (4) at the output of a capacitor (5) carrying a video signal is connected to a reference voltage source (1, 2). The use of a voltage source (1, 2) whose impedance depends on the direction of the current which it supplies, makes it possible to connect the conductor (4) to the voltage source (1, 2) during the whole duration of a line flyback, instead of being obliged to use a special pulse occurring solely at the end of the line flyback time. In the case of positive white, for example, a positive current supply part of the voltage source (2) having a high impedance sends a positive supply current to the conductor (4) carrying the video signal, and a low-impedance negative current supply part (1) connects this conductor to ground.

Abstract: A substantially digital circuit for correcting phase deviation which comprises a phase comparison stage and a synchronizing control stage. The phase comparison stage includes a reference oscillator, a frequency divider connected to the output of the oscillator and whose output signals constitute the useful line deflection drive signals, as well as a phase comparator comprising a logic circuit and a counter. The logic circuit receives the output signals of the frequency divider and the line synchronizing signals and the counter, which is connected to the output of the oscillator produces a signal which is representative of the phase deviation detected in control stage, the latter comprising a state detector for detecting the synchronized state, in which the phase deviation detected is below a limit value or the unsynchronized state and a correction signal generator for controlling the division ratio of the frequency divider.