Patents by Inventor ALAIN G. RWABUKAMBA

ALAIN G. RWABUKAMBA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Testing mechanism for a proximity fail probability of defects across integrated chips
    Patent number: 10768226
    Abstract: According to an embodiment, a testing mechanism determines a status of circuits within a chip by analyzing fail signatures on a by-level basis to identify a high probability defect area within the chip. The testing mechanism further determines a whether functionally needed circuitry of the chip intersects with the high probability defect area within the chip and determines the status of the circuits in response to the determining of whether the functionally needed circuitry intersects with the high probability defect area.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: September 8, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kirk D. Peterson, Alain G. Rwabukamba, Andrew A. Turner
  • TESTING MECHANISM FOR A PROXIMITY FAIL PROBABILITY OF DEFECTS ACROSS INTEGRATED CHIPS
    Publication number: 20180372799
    Abstract: According to an embodiment, a testing mechanism determines a status of circuits within a chip by analyzing fail signatures on a by-level basis to identify a high probability defect area within the chip. The testing mechanism further determines a whether functionally needed circuitry of the chip intersects with the high probability defect area within the chip and determines the status of the circuits in response to the determining of whether the functionally needed circuitry intersects with the high probability defect area.
    Type: Application
    Filed: August 30, 2018
    Publication date: December 27, 2018
    Inventors: Kirk D. Peterson, Alain G. Rwabukamba, Andrew A. Turner
  • Testing mechanism for a proximity fail probability of defects across integrated chips
    Patent number: 10114071
    Abstract: According to an embodiment, a testing mechanism determines a status of circuits within a chip by analyzing fail signatures on a by-level basis to identify a high probability defect area within the chip. The testing mechanism further determines a whether functionally needed circuitry of the chip intersects with the high probability defect area within the chip and determines the status of the circuits in response to the determining of whether the functionally needed circuitry intersects with the high probability defect area.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: October 30, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kirk D. Peterson, Alain G. Rwabukamba, Andrew A. Turner
  • TESTING MECHANISM FOR A PROXIMITY FAIL PROBABILITY OF DEFECTS ACROSS INTEGRATED CHIPS
    Publication number: 20170307685
    Abstract: According to an embodiment, a testing mechanism determines a status of circuits within a chip by analyzing fail signatures on a by-level basis to identify a high probability defect area within the chip. The testing mechanism further determines a whether functionally needed circuitry of the chip intersects with the high probability defect area within the chip and determines the status of the circuits in response to the determining of whether the functionally needed circuitry intersects with the high probability defect area.
    Type: Application
    Filed: April 26, 2016
    Publication date: October 26, 2017
    Inventors: KIRK D. PETERSON, ALAIN G. RWABUKAMBA, ANDREW A. TURNER