Abstract: Described is a high-speed/low-speed interface for data processing systems which interface may be implemented on a single LSI MOS chip having a first portion fabricated to include high-speed circuitry to be clocked by a high-speed clock, a second portion fabricated to include low-speed circuitry to be clocked by a low-speed clock, and a third portion formed to include interface circuitry for transferring the data between the other two portions. The described embodiment relates to a two-phase clock system in which the high-speed clocks have a fixed phase relationship to the low-speed clocks and have a pulse repetition frequency which is a whole number multiple of the low-speed clocks. The described single chip may be adapted for one-speed applications by merely connecting together the corresponding phases of the high-speed and low-speed clock input terminals.