Abstract: A barrel shifter circuit is provided for use with the arithmetic and logic units of a computer. The circuit includes a generator of a parity word composed of parity bits, each associated with one of a plurality of groups of n bits, each group of n bits being obtained by partitioning input words A and B. The circuit also includes a parity matrix associated with a shift matrix for producing the parity bits of the groups of n consecutive bits that constitute an output word S, provided via parity output lines Q.

Abstract: A system as proposed for calculating the parity bits (PS) of a sum (S) of two numbers (A, B). One parity bit (PA, PB, PS) is associated with each group of m bits (a.sub.i, b.sub.i, s.sub.i) extracted from the numbers (A, B) and the sum (S). For each group, one system for calculating the parity bit (PC) associated with the corresponding group extracted from the carry word formed at the time of the addition is provided. This system includes the following:a first stage (11) for calculating, for every i included between 1 and m-1, the values:p.sub.i =a.sub.i .sym.b.sub.ig.sub.i =a.sub.i .multidot.b.sub.iwhere .sym. indicates the EXCLUSIVE OR operation.a first operator (41a) for calculating, for every i included between 1 and m-1, the values P.sub.i and the values G.sub.i verifying the following recurring logical equations:P.sub.i =p.sub.i .multidot.P.sub.i-1, with P.sub.1 =p.sub.1G.sub.i =g.sub.i +p.sub.i .multidot.G.sub.i-1, with G.sub.1 =g.sub.1a second operator (41b) for calculating the following:Y=G.sub.1 .