Abstract: Embodiments described herein describe a network tester that is configured to perform packet modification at an egress pipeline of a programmable packet engine. A packet stream is received at an egress pipeline of an output port of the programmable packet engine, wherein the output port includes a packet modifier. Packets of the packet stream are modified at the packet modifier. The packet stream including modified packets is transmitted through an egress pipeline of the output port.

Abstract: Some embodiments provide a method for a hardware forwarding element. Based on a set of characteristics of a packet, the method determines to copy a packet to a particular temporary storage of a set of temporary storages of the hardware forwarding element. Based on a property of the particular temporary storage, the method stores only a particular portion of the packet in the particular temporary storage. A same size portion of each packet copied to the particular temporary storage is stored in the particular temporary storage.

Abstract: Some embodiments provide a method for a network forwarding integrated circuit (IC). The method receives packet data with an instruction to copy a portion of the packet data to a temporary storage of the network forwarding IC. The portion is larger than a maximum entry size of the temporary storage. The method generates a header for each of multiple packet data sections for storage in entries of the temporary storage, with each packet data section including a sub-portion of the packet data portion. The method sends the packet data sections with the generated headers to the temporary storage for storage in multiple separate temporary storage entries.

Abstract: Some embodiments provide a method for a hardware forwarding element. Based on a set of characteristics of a packet, the method determines to copy a packet to a particular temporary storage of a set of temporary storages of the hardware forwarding element. Based on a property of the particular temporary storage, the method stores only a particular portion of the packet in the particular temporary storage. A same size portion of each packet copied to the particular temporary storage is stored in the particular temporary storage.

Abstract: Embodiments described herein describe a network tester that is configured to perform packet modification at an egress pipeline of a programmable packet engine. A packet stream is received at an egress pipeline of an output port of the programmable packet engine, wherein the output port includes a packet modifier. Packets of the packet stream are modified at the packet modifier. The packet stream including modified packets is transmitted through an egress pipeline of the output port.

Abstract: Some embodiments provide a method for a hardware forwarding element. Based on a set of characteristics of a packet, the method determines to copy a packet to a particular temporary storage of a set of temporary storages of the hardware forwarding element. Based on a property of the particular temporary storage, the method stores only a particular portion of the packet in the particular temporary storage. A same size portion of each packet copied to the particular temporary storage is stored in the particular temporary storage.

Abstract: Some embodiments of the invention provide a novel method and chip design for a forwarding chip, that decouples input-output (IO) technology requirements from the technology used in a high bandwidth switching ASIC. In some embodiments, a main die including a latest generation switching chip is coupled to a set of IO dies (e.g., SerDes dies). The main die, in some embodiments, uses a latest technology (e.g., 7 nm nodes) while the IO dies, in some embodiments, use a more mature technology (e.g., 16 nm nodes). Some embodiments provide multiple IO dies that each provide connectivity to external components to the high bandwidth switching ASIC (e.g., a core ASIC die). The multiple dies are mounted on a silicon interposer, in some embodiments, using microbumps to make the connections between the dies and the silicon interposer. Additional connections to the pad are made from each die including to general purpose input-output (GPIO) connections.

Abstract: Some embodiments of the invention provide a novel method and chip design for a forwarding chip, that decouples input-output (IO) technology requirements from the technology used in a high bandwidth switching ASIC. In some embodiments, a main die including a latest generation switching chip is coupled to a set of IO dies (e.g., SerDes dies). The main die, in some embodiments, uses a latest technology (e.g., 7 nm nodes) while the IO dies, in some embodiments, use a more mature technology (e.g., 16 nm nodes). Some embodiments provide multiple IO dies that each provide connectivity to external components to the high bandwidth switching ASIC (e.g., a core ASIC die). The multiple dies are mounted on a silicon interposer, in some embodiments, using microbumps to make the connections between the dies and the silicon interposer. Additional connections to the pad are made from each die including to general purpose input-output (GPIO) connections.

Abstract: Some embodiments provide a method for a hardware forwarding element. Based on a set of characteristics of a packet, the method determines to copy a packet to a particular temporary storage of a set of temporary storages of the hardware forwarding element. Based on a property of the particular temporary storage, the method stores only a particular portion of the packet in the particular temporary storage. A same size portion of each packet copied to the particular temporary storage is stored in the particular temporary storage.

Abstract: This switch comprises a central buffer memory (30) for temporarily storing the data traffic which it receives, the time for performing the routings and for carrying out the resendings of the messages that it receives. It is noteworthy in that its central buffer memory (30) and the accesses to this buffer memory (30) by its various input/output ports are managed by a sequencer (40) in such a way as to have an implicit measure of the timescale for storing the messages in the central buffer memory (30) and to minimize the number of switchings which generate consumption and electromagnetic disturbances. Advantageously, the buffer memory is embodied with the aid of several modules (A, B, C, D) operating in parallel.

Abstract: This method consists in making a routing automaton carry out verifications on the integrity of the packets arriving at the packet switch, their periods of stay in the packet switch, their matching with the virtual paths that they claim to take as well as the routings proper, within the packet switch, of the datagrams that have satisfactorily undergone the verification. The routing automaton is provided with a random access memory of instructed values containing a table of virtual path local descriptors. The processing time of the automaton is divided into a repetitive sequence of time slots individually allocated to the different input ports of the packet switch.

Abstract: This switch comprises a central buffer memory (30) for temporarily storing the data traffic which it receives, the time for performing the routings and for carrying out the resendings of the messages that it receives. It is noteworthy in that its central buffer memory (30) and the accesses to this buffer memory (30) by its various input/output ports are managed by a sequencer (40) in such a way as to have an implicit measure of the timescale for storing the messages in the central buffer memory (30) and to minimize the number of switchings which generate consumption and electromagnetic disturbances. Advantageously, the buffer memory is embodied with the aid of several modules (A, B, C, D) operating in parallel.

Abstract: This method consists in making a routing automaton (50) carry out verifications on the integrity of the packets arriving at the packet switch (1), their periods of stay in the packet switch (1), their matching with the virtual paths that they claim to take as well as the routings proper, within the packet switch (1), of the datagrams that have satisfactorily undergone the verification. The routing automaton (50) is provided with a random access memory of instructed values (60) containing a table of virtual path local descriptors. The processing time of the automaton is divided into a repetitive sequence of time slots individually allocated to the different input ports (21, 22, 23) of the packet switch (1).