Abstract: A reading circuit comprises a first and second cascode circuit and a first and second current mirror. The first cascode circuit can be connected to a bit line of a memory cell and the second cascode circuit can be connected to a reference bit line of a reference cell. The first output terminals of the first and second cascode circuits are connected to first terminals of the first and second current mirrors, respectively. The second output terminals of the first and second cascode circuits are connected to the second terminals of the second and first current mirrors, respectively. A tri-state buffer is coupled between the second terminals of the first and second current mirrors said buffer having bit invert capabilities.

Abstract: In order to provide a reduction in power wasted by leakage currents in a CMOS SRAM without unduly compromising speed performance or increasing the chance of data errors, the invention proposes a device and method for selectively deactivating peripheral parts of the memory when the memory is in a stand-by mode. The device proposed for implementing the invention comprises a memory made up of cells (10) and peripheral circuits (20), and a transistor switch (30A—30I) capable of interrupting the power supply to the peripheral circuits (20) depending on the voltage supplied to it on a power down (PD) select line and thus reducing the power wasted by leakage currents in the peripheral circuits (20). The transistor switch (30A—30I) cooperates with the peripheral circuits (20) to ensure that data integrity is maintained in a stand-by mode and that a high operating speed is possible when either writing to or reading from the memory cells (10).