Abstract: In the method of manufacturing a vertical field effect transistor, the gate region situated on either side of the source region projecting from a main face of a semiconductive substrate consists in implanting ions on either side of the source region to form a junction, and in forming a metal silicide on the gate region made in this way. Such a transistor is particularly suitable for being integrated in various MOS technologies, and in particular in CMOS.

Abstract: A bipolar transistor comprising a semiconductor substrate, of a first conductivity type, a retrograde well serving as the collector and having a second conductivity type opposite to the first, a base active region having a first conductivity type, a region serving as an emitter of the second conductivity type, the regions being bordered on either side by insulating regions. According to the invention, the transistor includes at least one second conductivity type zone serving as the collector contact, located in a region of the retrograde well at a distance from the base zone and extending away from said base zone no further than level with the insulating zone. The invention is applicable to making BI-MOS or BI-CMOS circuits.