Abstract: Briefly, a memory device comprising a beta phase tungsten seed layer is disclosed.

Abstract: Briefly, a memory device comprising a beta phase tungsten seed layer is disclosed.

Abstract: A method is provided which includes forming a hardmask feature adjacent to a patterned sacrificial structure of a semiconductor topography, selectively removing the patterned sacrificial structure to expose a lower layer and etching exposed portions of the lower layer in alignment with the hardmask feature. In some embodiments, forming the hardmask feature may include conformably depositing a hardmask material above the patterned sacrificial structure and lower layer as well as blanket etching the hardmask material such that upper surfaces of the patterned sacrificial structure and portions of the lower layer are exposed and portions of the hardmask material remain along sidewalls of the patterned sacrificial structure. The method may be applied to produce an exemplary semiconductor topography including a plurality of gate structures each having a width less than approximately 70 nm, wherein a variation of the widths among the plurality of gate structures is less than approximately 10%.

Abstract: In one embodiment, a method of fabricating an integrated circuit includes the steps of: (i) forming composite spacers on sidewalls of a transistor gate, each of the composite spacers comprising a first liner having a stepped portion and a disposable spacer material over the stepped portion; (ii) forming a source/drain region by performing ion implantation through a portion of the first liner over the source/drain region; (iii) replacing the disposable spacer material with a second liner formed over the first liner after forming the source/drain region; (iv) forming a pre-metal dielectric over the second liner; and (v) forming a self-aligned contact through the pre-metal dielectric. Among other advantages, the method allows for an increased contact area for a self-aligned contact.

Abstract: A method is provided, which includes patterning a stack of layers spaced below a sacrificial hardmask layer. In some embodiments, the method may include patterning a lower hardmask layer arranged above the stack of layers. Such a patterning process may include removing the entire sacrificial hardmask layer. For example, the method may include patterning an upper portion of the stack of layers using the sacrificial hardmask layer as a first mask and patterning a lower portion of the stack of layers using the lower hardmask layer as a second mask. Consequently, a semiconductor topography is provided herein which includes a sacrificial hardmask layer arranged above a plurality of layers. Such a sacrificial hardmask layer may include a material with substantially different etch characteristics than one or more upper layers of the plurality of layers and substantially similar etch characteristics as one or more lower layers of the plurality of layers.

Abstract: A method is provided for fabricating a device, which includes device components and spacings that may each have a final dimension that is smaller than a minimum dimension obtainable by a photolithography process used to form the device components. In particular, the method may include patterning an upper layer of the semiconductor topography using the photolithography process to form a device mask having dimensions substantially equal to or greater than the minimum dimension. The method may further include trimming the device mask and forming a semiconductor structure in alignment with the trimmed device mask. In addition, the method may include patterning the semiconductor structure to form device components and spacings therebetween. In general, patterning the semiconductor structure may include tapering a first layer of the semiconductor structure and removing an exposed portion of a second layer of the semiconductor structure.