Abstract: A battery management system, BMS, integrated circuit, IC, (102) for a battery pack. The battery pack (101) comprises a sequence of battery cells connected in series; and a sequence of battery-cell-connection-nodes between adjacent battery cells. The BMS IC (102) comprises: a sequence of cell-measuring-pins (104) for connecting to corresponding battery-cell-connection-nodes; a plurality of bi-directional ESD protection elements (105), each one connected between a pair of adjacent cell-measuring-pins (104) in the sequence; a sequence of cell-balancing-pins (106) for connecting to corresponding battery-cell-connection-nodes; and a plurality of dual polarity switches (107), each one connected between a pair of adjacent cell-balancing-pins in the sequence.

Abstract: An ESD protection device for protecting an integrated circuit against an ESD event includes a first terminal coupled to an input/output pad of the IC, a second terminal coupled to a reference or ground voltage, a silicon-controlled rectifier device having an anode connected to the first terminal and a cathode connected to the reference or ground voltage, and a pnp transistor coupled in parallel with the SCR device. The pnp transistor has an emitter coupled to the first terminal, a collector coupled to the second terminal, and a base coupled to a gate of the SCR. The pnp transistor includes a contact region formed at a first side of a substrate, the first contact region being surrounded by an STI layer formed at the first side of the substrate. An insulation structure is formed at an intersection of the first contact region and the STI layer.

Abstract: An electrostatic discharge (ESD) protection device includes a first bi-directional silicon controlled rectifier having a doped well of a first conductivity type, a buried doped layer having a second conductivity type opposite the first conductivity type, first and second highly doped regions of the second conductivity type in the doped well, and a third highly doped region of the first conductivity type in the doped well. The first, second and third highly doped regions are connected to a first node. A first transistor in the doped well includes an emitter coupled to the first highly doped region, a collector coupled to a conductive line in the buried doped layer, and a base coupled to the third highly doped region. A second transistor in the doped well includes an emitter coupled to the second highly doped region, a collector coupled to the conductive line in the buried doped layer, and a base coupled to the third highly doped region.

Abstract: An ESD protection device for protecting an integrated circuit (IC) against an ESD event includes a first terminal coupled to an input/output pad of the IC, a second terminal coupled to a reference or ground voltage, a silicon-controlled rectifier (SCR) device having an anode connected to the first terminal and a cathode connected to the reference or ground voltage, and a pnp transistor coupled in parallel with the SCR device. The pnp transistor has an emitter coupled to the first terminal, a collector coupled to the second terminal, and a base coupled to a gate of the SCR. The pnp transistor includes a contact region formed at a first side of a substrate, the first contact region being surrounded by an STI layer formed at the first side of the substrate. An insulation structure is formed at an intersection of the first contact region and the STI layer.

Abstract: An electrostatic discharge (ESD) protection device includes a first bi-directional silicon controlled rectifier having a doped well of a first conductivity type, a buried doped layer having a second conductivity type opposite the first conductivity type, first and second highly doped regions of the second conductivity type in the doped well, and a third highly doped region of the first conductivity type in the doped well. The first, second and third highly doped regions are connected to a first node. A first transistor in the doped well includes an emitter coupled to the first highly doped region, a collector coupled to a conductive line in the buried doped layer, and a base coupled to the third highly doped region. A second transistor in the doped well includes an emitter coupled to the second highly doped region, a collector coupled to the conductive line in the buried doped layer, and a base coupled to the third highly doped region.

Abstract: Apparatus for testing a device by delivering an electrostatic discharge signal to one or more device terminals, comprising a first part configured for mechanically mounting the device and comprising one or more first part connectors for electrically coupling to the one or more device terminals and thus providing electrical access to the one or more device terminals, a second part comprising one or more second part connectors configured for electrically coupling the one or more first part connectors to the one or more second part connectors for testing the device via the second part connectors, and a guide arranged for mechanically moving the first part relative to the second part. The guide is configured to physically disconnect the one or more first part connectors from the one or more second part connectors while the electrostatic discharge signal is delivered to the one or more device terminals.

Abstract: An integrated circuit die includes a stack of a substrate and multiple layers extending in parallel to the substrate. A number of integrated electronic components is formed in the stack, and connected to form an electronic circuit. The electronic circuit comprises a first electric contact, a second electric contact, and a coupling which couples the electric strips electrically to each other. The coupling includes a circuit via which extends through at least two of the layers. The die further includes an integrated current sensor having a coil arrangement for sensing a current flowing through a part of the electronic circuit. The coil arrangement is magnetically coupled to the circuit via over at least a part of a length of the circuit via to sensing a magnetic flux through the circuit via. A measurement unit can measure a parameter of the coil arrangement representative of a current flowing through the circuit via.

Abstract: A method of testing a semiconductor device against electrostatic discharge includes operating the semiconductor device, and, while operating the semiconductor device, monitoring a functional performance of the semiconductor device. The monitoring includes monitoring one or more signal waveforms of respective one or more signals on respective one or more pins of the semiconductor device to obtain one or more monitor waveforms, and monitoring one or more register values of one or more registers of the semiconductor device to obtain one or more monitor register values as function of time. The method includes applying an electrostatic discharge event to the semiconductor device while monitoring the functional performance of the semiconductor device. The method can further comprise determining a functional change from the one or more monitor waveforms and the one or more monitor register values as function of time.

Abstract: A semiconductor device is provided which comprises an ESD protection device. The structure of the semiconductor device comprises a p-doped isolated region in which a structure is manufactured which operates as a Silicon Controlled Rectifier which is coupled between an I/O pad and a reference voltage or ground voltage. The semiconductor device also comprises a pnp transistor which is coupled parallel to the Silicon Controlled Rectifier. The base of the transistor is coupled to the gate of the Silicon Controlled Rectifier. In an optional embodiment, the base and gate are also coupled to the I/O pad.

Abstract: A current sensor comprises a current carrying trace located within a substrate; and a sensing trace located within the substrate proximate to the current carrying trace; wherein the sensing trace detects an electromagnetic force (emf) generated by magnetic flux inductively coupled from the current carrying trace for transmitting to a current sensing device.

Abstract: A semiconductor device is provided which comprises an ESD protection device. The structure of the semiconductor device comprises a p-doped isolated region in which a structure is manufactured which operates as a Silicon Controlled Rectifier which is coupled between an I/O pad and a reference voltage or ground voltage. The semiconductor device also comprises a pnp transistor which is coupled parallel to the Silicon Controlled Rectifier. The base of the transistor is coupled to the gate of the Silicon Controlled Rectifier. In an optional embodiment, the base and gate are also coupled to the I/O pad.

Abstract: Apparatus for testing a device by delivering an electrostatic discharge signal to one or more device terminals, comprising a first part configured for mechanically mounting the device and comprising one or more first part connectors for electrically coupling to the one or more device terminals and thus providing electrical access to the one or more device terminals, a second part comprising one or more second part connectors configured for electrically coupling the one or more first part connectors to the one or more second part connectors for testing the device via the second part connectors, and a guide arranged for mechanically moving the first part relative to the second part. The guide is configured to physically disconnect the one or more first part connectors from the one or more second part connectors while the electrostatic discharge signal is delivered to the one or more device terminals.

Abstract: A semiconductor device is provided which comprises an ESD protection device. The structure of the semiconductor device comprises a p-doped isolated region in which a structure is manufactured which operates as a Silicon Controlled Rectifier which is coupled between an I/O pad and a reference voltage or ground voltage. The semiconductor device also comprises a pnp transistor which is coupled parallel to the Silicon Controlled Rectifier. The base of the transistor is coupled to the gate of the Silicon Controlled Rectifier. In an optional embodiment, the base and gate are also coupled to the I/O pad.

Abstract: An electrostatic discharge, ESD, protection circuit arrangement is connectable to a first pin and a second pin of an electronic circuit and arranged to at least partly absorb an ESD current entering the electronic circuit through at least one of the first pin or the second pin during an ESD stress event. The protection circuit arrangement comprises a first ESD protection circuit arranged to absorb a first portion of the ESD current during a first part of the ESD stress event during which first part a level of the ESD current exceeds a predetermined current threshold; and a second ESD protection circuit arranged to absorb a second portion of the ESD current, the second portion having a current level below the current threshold, at least during a second part of the ESD stress event. The second ESD protection circuit comprises a current limiting circuit arranged to limit a current through at least a portion of the second ESD protection circuit to the current threshold.

Abstract: An integrated circuit die includes a stack of a substrate and multiple layers extending in parallel to the substrate. A number of integrated electronic components is formed in the stack, and connected to form an electronic circuit. The electronic circuit comprises a first electric contact, a second electric contact, and a coupling which couples the electric strips electrically to each other. The coupling includes a circuit via which extends through at least two of the layers. The die further includes an integrated current sensor having a coil arrangement for sensing a current flowing through a part of the electronic circuit. The coil arrangement is magnetically coupled to the circuit via over at least a part of a length of the circuit via to sensing a magnetic flux through the circuit via. A measurement unit can measure a parameter of the coil arrangement representative of a current flowing through the circuit via.

Abstract: A method of testing a semiconductor device against electrostatic discharge includes operating the semiconductor device, and, while operating the semiconductor device, monitoring a functional performance of the semiconductor device. The monitoring includes monitoring one or more signal waveforms of respective one or more signals on respective one or more pins of the semiconductor device to obtain one or more monitor waveforms, and monitoring one or more register values of one or more registers of the semiconductor device to obtain one or more monitor register values as function of time. The method includes applying an electrostatic discharge event to the semiconductor device while monitoring the functional performance of the semiconductor device. The method can further comprise determining a functional change from the one or more monitor waveforms and the one or more monitor register values as function of time.

Abstract: A current sensor comprises a current carrying trace located within a substrate; and a sensing trace located within the substrate proximate to the current carrying trace; wherein the sensing trace detects an electromagnetic force (emf) generated by magnetic flux inductively coupled from the current carrying trace for transmitting to a current sensing device.

Abstract: A semiconductor device is provided which comprises an ESD protection device. The structure of the semiconductor device comprises a p-doped isolated region in which a structure is manufactured which operates as a Silicon Controlled Rectifier which is coupled between an I/O pad and a reference voltage or ground voltage. The semiconductor device also comprises a pnp transistor which is coupled parallel to the Silicon Controlled Rectifier. The base of the transistor is coupled to the gate of the Silicon Controlled Rectifier. In an optional embodiment, the base and gate are also coupled to the I/O pad.

Abstract: An electrostatic discharge, ESD, protection circuit arrangement is connectable to a first pin and a second pin of an electronic circuit and arranged to at least partly absorb an ESD current entering the electronic circuit through at least one of the first pin or the second pin during an ESD stress event. The protection circuit arrangement comprises a first ESD protection circuit arranged to absorb a first portion of the ESD current during a first part of the ESD stress event during which first part a level of the ESD current exceeds a predetermined current threshold; and a second ESD protection circuit arranged to absorb a second portion of the ESD current, the second portion having a current level below the current threshold, at least during a second part of the ESD stress event. The second ESD protection circuit comprises a current limiting circuit arranged to limit a current through at least a portion of the second ESD protection circuit to the current threshold.