Abstract: A method and a system architecture making it possible to establish in a dynamic manner one or more encrypted tunnels on constrained-band communication networks is provided. It makes it possible in particular to encrypt one or more data streams while guaranteeing the quality of services on the constrained-band systems, in particular for encrypted streams of voice over IP type (Internet protocol) or of data type. These tunnels are thus adapted most suitably to the useful data streams while making it possible to control and assign the necessary values for the quality of service or QoS on these networks.

Abstract: Device for implementing modular multiplication, characterized in that it comprises at least one computation cell comprising a multiplier-adder comprising p pipelined logic-register pairs, receiving several digits to be added together and multiplied, at least two outputs corresponding to the low order and to the high order, an adder receiving the two outputs of the multiplier-adder, the number p being chosen in such a way that the maximum frequency of the multiplier-adder is greater than or equal to the maximum frequency of the adder.

Abstract: This invention concerns a Montgomery masked modular multiplication process and the associated device. The modular multiplication, in congruence n, includes at least a stage generating a pseudo-random number z and a stage adding to the result the product of the said number by n. The invention applies in particular to the securing of processors dedicated to cryptographic calculations.

Abstract: This invention concerns an improved modular reduction device. The modular reduction device includes a multiplier using an alternative of the Montgomery multiplication process using a high numeration base r with r being equal to or greater than 4. It applies more particularly to the calculation components used for asymmetrical cryptography.

Abstract: Device for implementing modular multiplication, characterized in that it comprises at least one computation cell comprising a multiplier-adder comprising p pipelined logic-register pairs, receiving several digits to be added together and multiplied, at least two outputs corresponding to the low order and to the high order, an adder receiving the two outputs of the multiplier-adder, the number p being chosen in such a way that the maximum frequency of the multiplier-adder is greater than or equal to the maximum frequency of the adder.