Abstract: Method for processing a sequence of digital signal samples including a first sub-sequence and a second sub-sequence. Forming a first block of samples comprising the first sub-sequence and a second block of samples comprising header samples followed by the second sub-sequence. Demodulating the first block of samples through a digital demodulator to produce a first block of symbols, and the second block of digital signal samples through a second digital demodulator to produce a second block of symbols. The second demodulator implementing a carrier synchronisation or symbol rate synchronisation starting with the header samples, which comprise samples in a number adapted in such a way that the synchronisation is effective before the second demodulator demodulates the second sub-sequence. Reconstructing a sequence of symbols by concatenating the first symbol block with the second symbol block.

Abstract: A method of date-stamping reception of digital data of a signal coherently modulating the carrier or sub-carrier, and utilizing the properties of such a modulation to improve the date-stamping thereof. Thereby accurately correcting the date-stamping of a pilot sequence (known pattern), and reducing the variance on the date-stamping of the transitions of the bits.

Abstract: The invention relates to a method of date-stamping reception of digital data of a modulated signal, said signal resulting from the modulation of a carrier or sub-carrier by a digital signal, the bitrate of symbols of the digital signal being an integer sub-multiple N of the frequency of the carrier or sub-carrier, said method comprising the steps consisting in: —coherent demodulation by means of a phase loop of a plurality of samples sm(k) of the modulated signal and obtaining of a plurality of demodulated samples sdm(k) and of the phase of the reconstructed carrier; —association of the plurality of demodulated samples sdm(k) with the simultaneous phase ?(k) of the reconstructed carrier —determination of a plurality of dates of passage to a determined value ?0 of the phase of the reconstructed carrier, relative to the date of reception of at least one sample sm(k), according to a time shift during which the carrier rotates from ?(k) to ?0.

Abstract: Method for processing a sequence of digital signal samples comprising a first sub-sequence and a second sub-sequence, said method comprising: forming (106) a first block of samples comprising the first sub-sequence and a second block of samples comprising header samples followed by the second sub-sequence; demodulating (108) the first block of samples through a digital demodulator to produce a first block of symbols, and the second block of digital signal samples through a second digital demodulator to produce a second block of symbols, the second demodulator implementing a carrier synchronisation or symbol rate synchronisation starting with the header samples (E6-E9), which comprise samples in a number adapted in such a way that the synchronisation is effective before the second demodulator demodulates the second sub-sequence; and reconstructing (114) a sequence of symbols by concatenating the first symbol block with the second symbol block.

Abstract: The invention relates to a radio communication receiver receiving a radio signal (S) including a main polarisation (MAIN-POL) and a secondary polarisation (X-POL) orthogonal to the main polarisation (MAIN-POL), the receiver including: a unit (1) for receiving the main polarisation (MAIN-POL) and the secondary polarisation of the received signal, synchronised as a carrier frequency with the main polarisation (MAIN-POL); a unit (2) for cancelling out the secondary polarisation synchronised with the main polarisation (MAIN-POL) and configured to suppress, from the received signal (S), the interference due to the secondary polarisation (X-POL), the unit (2) for cancelling out the secondary polarisation including a filtering unit (21) that receives the main polarisation (MAIN-POL) and the secondary polarisation (X-POL) as input; a unit (3) for demodulating the filtered signal, located downstream of the cancellation unit and configured to calculate carrier frequency error information and to communicate same by feed

Abstract: The invention relates to a radio communication receiver receiving a radio signal (S) including a main polarisation (MAIN-POL) and a secondary polarisation (X-POL) orthogonal to the main polarisation (MAIN-POL), the receiver including: a unit (1) for receiving the main polarisation (MAIN-POL) and the secondary polarisation of the received signal, synchronised as a carrier frequency with the main polarisation (MAIN-POL); a unit (2) for cancelling out the secondary polarisation synchronised with the main polarisation (MAIN-POL) and configured to suppress, from the received signal (S), the interference due to the secondary polarisation (X-POL), the unit (2) for cancelling out the secondary polarisation including a filtering unit (21) that receives the main polarisation (MAIN-POL) and the secondary polarisation (X-POL) as input; a unit (3) for demodulating the filtered signal, located downstream of the cancellation unit and configured to calculate carrier frequency error information and to communicate same by feed

Abstract: A method for printing a plurality of base materials with a device including a plurality of print units, a distribution system for distributing the base materials in the print units and a recovery system for recovering the printed base materials after each of the materials has passed through a print unit, including distributing the base materials in the print units through a top end portion of the print units with the distribution system; and recovering the printed base materials after each of the base materials has passed through a print unit through a bottom end portion of the print units with the recovery system.

Abstract: An asynchronous FIFO (firstin, firstout) device suitable for use as a buffer comprises a stack having a plurality of sections. Each section has a data storage register and a control subassembly. Each assembly is associated with one of said data storage registers. A single data input is connected to the first data storage register. The data storage registers have a transparent condition and a latched condition and each subassembly comprises a 2-to-1 MUX (multiplexer) having a first input connected to receive a logic signal indicative of the condition of the preceding subassembly, a second input connected to receive a logic signal indicative of the condition of the following subassembly and an output connected to the associated storage register. The MUX is constructed to deliver on its output a signal representative of the condition of the subassembly and its internal connections are determined by the logic level of the output signal of the MUX.

Abstract: The method consists in converting an inputting multiframe including of M frames each having words assigned respectively to C multiplexed digital channels into an outgoing multiframe including of C packets each having M words of a respective channel. So as to only use a single memory, a word having a given rank in the outgoing multiframe and a word having said given rank in the inputting multiframe are read and written consecutively in a same cell of the single memory. The memory has a capacity at least equal to MC word cells. The MC cells are addressed according to an address order rebecoming identical to itself after a cycle of N multiframe periods, where N is the smallest integer so that C.sup.N .tbd.1 (mod (MC-1)).

Abstract: A memory arrangement for temporary data storage of the FIFO type includes a random access memory associated with an input buffer register and two output buffer registers. The registers may consist of transparent flip-flops. The control system for the arrangement is provided for authorizing reading out from the output register at any time independently of the writing times in the random access memory and for causing reading out from the random access memory in response to an indication that the first output register is empty. A priority input of said control system makes it possible to interrupt a reading or writing operation when a request for the other operation is received. The control system has means for detecting full condition and empty condition of the FIFO. The control system further includes a handling logic for the output registers.

Abstract: The system switches data packets, with headers, from input junctions to output junctions. The series incoming packets are converted into parallel packets. The headers of each incoming packet and the identity of the involved input junction are transferred to the address inputs of a control memory. The control memory supplies a new header which is assigned to the incoming packet, in replacement of the original header, in order to form the parallel outgoing packet with the remaining part of the incoming packet. A buffer memory is cyclically enabled for writing, in order to store the outgoing packets. Each parallel packet read out of the buffer memory is converted into a series packet. Queues store the addresses of a packet in the buffer memory, and are selectively enabled for writing, depending on information from the control memory. Each queue is assigned to an output junction.

Abstract: A digital train is synchronized to correct the framing of received information. To this end, the transmitted digital train is timely structured into recurrent time intervals having a fixed length. The information to be transmitted is divided into blocks called packets, having the length of a time interval and comprising a field of data and a header used for identifying the packets. A digital transmission system with a TDM multiplex is divided into equal and recurrent time intervals, wherein the information is indexed by an associated explicit header, and wherein the absence of information in a time interval is indexed by a specific header which is not used elsewhere as a header. The recognition of a specific address is also used for synchronizing the alignment of the time intervals.