Abstract: A memory controller includes a generator circuit configured to generate a predetermined pattern of data, an address input, and a memory interface circuit. The memory interface circuit is configured to write the predetermined pattern of data to a memory at an address identified in the address input. The memory interface circuit is further configured to read a stored pattern of data from the memory at the address. The memory controller further includes an integrity checker circuit configured to compare the predetermined pattern of data and the stored pattern of data and identify an error of the memory based upon the comparison.

Abstract: A device comprises a detector configured to detect an event, and a selector coupled to the detector and configured to generate a signal in response to a detection of an event by the detector. The signal is operable to select a set of input/output (I/O) parameters from among first and second stored sets of parameters. The device also includes a configuration module coupled to the selector. The configuration module is configured to output the selected set of I/O parameters.

Abstract: A memory controller includes a generator circuit configured to generate a predetermined pattern of data, an address input, and a memory interface circuit. The memory interface circuit is configured to write the predetermined pattern of data to a memory at an address identified in the address input. The memory interface circuit is further configured to read a stored pattern of data from the memory at the address. The memory controller further includes an integrity checker circuit configured to compare the predetermined pattern of data and the stored pattern of data and identify an error of the memory based upon the comparison.

Abstract: A device comprises a detector configured to detect an event, and a selector coupled to the detector and configured to generate a signal in response to a detection of an event by the detector. The signal is operable to select a set of input/output (I/O) parameters from among first and second stored sets of parameters. The device also includes a configuration module coupled to the selector. The configuration module is configured to output the selected set of I/O parameters.

Abstract: A device comprises a detector configured to detect an event, and a selector coupled to the detector and configured to generate a signal in response to a detection of an event by the detector. The signal is operable to select a set of input/output (I/O) parameters from among first and second stored sets of parameters. The device also includes a configuration module coupled to the selector. The configuration module is configured to output the selected set of I/O parameters.

Abstract: A device comprises a detector configured to detect an event, and a selector coupled to the detector and configured to generate a signal in response to a detection of an event by the detector. The signal is operable to select a set of input/output (I/O) parameters from among first and second stored sets of parameters. The device also includes a configuration module coupled to the selector. The configuration module is configured to output the selected set of I/O parameters.

Abstract: A system includes one or more master modules configured to execute instructions embedded in non-transitory machine-readable media and controllable by a processor. The system also includes one or more peripheral modules that are configured to execute instructions embedded in non-transitory machine-readable media and controllable by the processor. The system also includes a system bus with instructions embedded in a non-transitory machine-readable medium and configured to allow data transfer between the processor and the one or more peripheral modules. A data processing module of the one or more peripheral modules includes a master interface and a slave interface. Both master and slave interfaces are coupled to the system bus.

Abstract: A system includes one or more master modules configured to execute instructions embedded in non-transitory machine-readable media and controllable by a processor. The system also includes one or more peripheral modules that are configured to execute instructions embedded in non-transitory machine-readable media and controllable by the processor. The system also includes a system bus with instructions embedded in a non-transitory machine-readable medium and configured to allow data transfer between the processor and the one or more peripheral modules. A data processing module of the one or more peripheral modules includes a master interface and a slave interface. Both master and slave interfaces are coupled to the system bus.

Abstract: A system includes one or more master modules configured to execute instructions embedded in non-transitory machine-readable media and controllable by a processor. The system also includes one or more peripheral modules that are configured to execute instructions embedded in non-transitory machine-readable media and controllable by the processor. The system also includes a system bus with instructions embedded in a non-transitory machine-readable medium and configured to allow data transfer between the processor and the one or more peripheral modules. A data processing module of the one or more peripheral modules includes a master interface and a slave interface. Both master and slave interfaces are coupled to the system bus.

Abstract: A variable architecture for random number generators is disclosed. In some implementations, the architecture of a random number generator may be varied based on microcontroller-specific data stored on the microcontroller. For example, a random number generator module may be embedded in a microcontroller circuit. The random number generator module may be designed to receive input from data sources in the circuit that contain microcontroller-specific data (e.g., a unique chip identifier, data carried in fuse bits). In some implementations, the architecture of the random number generator module may be adjusted or varied based on the microcontroller-specific data.

Abstract: A scrambler/descrambler module included in an integrated circuit device is operable for receiving a scrambling key and constant data that is unique to the integrated circuit device. The scrambler/descrambler module includes a first layer or circuit arrangement that uses a scrambling key to generate first scrambled data. The scrambler/descrambler module includes a second layer or second circuit arrangement that uses data that is unique to the integrated circuit device, and that is constant over the life of the integrated circuit device, to scramble the first scrambled data to generate second scrambled data.

Abstract: Various systems and methods for encrypting data are disclosed. In one aspect, the method includes receiving a memory address and a value to be written in the memory address. The method also includes encrypting the value using the memory address as an initial value for an encryption process. The method also includes storing the encrypted value in the memory address.

Abstract: A microcontroller includes a system bus matrix to connect various modules. The microcontroller also includes direct connections between modules. For example, the microcontroller may include a direct connection between a data processing module and a memory controller module to improve the transfer rate for data that is processed by the data processing module.

Abstract: An integrated circuit comprises a predefined logic area including a microprocessor coupled to a plurality of peripheral devices including an external bus interface over a system bus. A customizable logic area is accessible by the microprocessor over the system bus. A first I/O bus sends data to an external device. A second I/O bus receives data from an external device. A first set of multiplexers in the predefined logic area have first inputs coupled to an output of the external bus interface, second inputs coupled to the customizable logic area, and an output coupled to a first I/O bus. A second set of multiplexers in the predefined logic area have first inputs coupled to the customizable logic area, second inputs coupled to the second I/O bus, and an output coupled to an input of the external bus interface.

Abstract: A system includes one or more master modules configured to execute instructions embedded in non-transitory machine-readable media and controllable by a processor. The system also includes one or more peripheral modules that are configured to execute instructions embedded in non-transitory machine-readable media and controllable by the processor. The system also includes a system bus with instructions embedded in a non-transitory machine-readable medium and configured to allow data transfer between the processor and the one or more peripheral modules. A data processing module of the one or more peripheral modules includes a master interface and a slave interface. Both master and slave interfaces are coupled to the system bus.

Abstract: Various systems and methods for encrypting data are disclosed. In one aspect, the method includes receiving a memory address and a value to be written in the memory address. The method also includes encrypting the value using the memory address as an initial value for an encryption process. The method also includes storing the encrypted value in the memory address.

Abstract: An inappropriate-access module is incorporated in a computer system along with other computer system modules. The inappropriate-access module is connected to a read address decoder and controlling logic located within various other modules. The inappropriate-access module detects inappropriate read accesses or the occurrence of the inappropriate access during operations performed on related sensitive system resources in accompanying computer system modules. The inappropriate-access module produces an inappropriate-access flag, made available to the rest of the system, which invokes responses in the accompanying modules such as a halt in processing and protective measures for system resources. Additionally, a related logic block is able to detect the inappropriate access and produce an inappropriate-access trigger which causes a halt to processing within the logic block as well as in related system modules.

Abstract: A variable architecture for random number generators is disclosed. In some implementations, the architecture of a random number generator may be varied based on microcontroller-specific data stored on the microcontroller. For example, a random number generator module may be embedded in a microcontroller circuit. The random number generator module may be designed to receive input from data sources in the circuit that contain microcontroller-specific data (e.g., a unique chip identifier, data carried in fuse bits). In some implementations, the architecture of the random number generator module may be adjusted or varied based on the microcontroller-specific data.

Abstract: A microcontroller that includes logic to provide a uniform overall power consumption current of parts of the microcontroller generated by sequential element switching is disclosed. For example, the number of sequential elements switching at the triggering edge of the clock is calculated to determine a number of switching elements. The number of switching elements is compared to the number of sequential elements of the circuitry. Additional sequential elements are added in the circuitry and are forced to switch so that the overall number of switching elements equals the number of sequential elements, excluding the additional sequential elements.

Abstract: The disclosed quadrature decoder filtering circuitry for motor control uses one quadrature signal to correct an error in the other quadrature signal, thus allowing a noisy signal due to large dust particles or scratches to be recovered. In some implementations, a system processing for quadrature signals comprises a first circuitry triggered by edges of a first quadrature signal to detect inactivity of a second quadrature signal during consecutive edges of the first quadrature signal. A second circuitry is operable to count the number of consecutive edges of the first quadrature signal during inactivity of the second quadrature signal. A third circuitry is operable to combine transitions of the first quadrature signal with the second quadrature signal during a period of time determined by the count value of the second circuitry.