Abstract: A digital data transmission system comprises at its input a higher order multiplexer receiving at least one stream of digitized data organized into blocks and at a specific timing, said multiplexer transmitting each block of data in a digital multiplex to the output of the transmission system via a digitized data transmission channel subject to a variable multiplexing delay. To reduce the low-frequency component of the jitter in a timing signal reconstituted at the output of the system, the multiplexing delay is measured for the current transmission of a block of data in the multiplex and the measured multiplexing delay is compared with a reference value to determine a multiplexing delay offset and if necessary to defer said current transmission. The measurement and comparison are repeated for the next transmission of a block of data in the multiplex using in the comparison the multiplexing offsets determined for previous transmissions.

Abstract: The switching device includes a multiplexer (2) and a control device (8). The multiplexer has a first input (Y.sub.i) for receiving a first digital signal (S1), a second input (Y.sub.j) for receiving a second digital signal (S2), an output to emit a resultant digital signal (SR), and at least one control input. The control device send signals to the multiplexer's control inputs for switching the multiplexer from the first input to the second input and to introduce during the switching a characteristic sequence into the multiplexer output. This sequence may, in particular, be produced by a clock signal generator connected to a third input of the multiplexer.

Abstract: The invention relates to a process for the transmission in blocks of digital information words with a correction capability. This process consists of transmitting in blocks digital information words, each information word having a length of n.sub.1 bits, in which with each sequence of n.sub.2 -k (n.sub.2 >k) of consecutive information words are associated k redundancy words of n.sub.1 bits each in which, for each order i (1<i<n.sub.2), the k bits of order i of the redundancy words are redundancy bits in accordance with a Hamming code (n.sub.2 0k, k). For each set of n.sub.2 linked words, each word is transmitted while being protected by an error detecting code. Several sets of linked words can be interlaced. The words of the same order or rank of each set form a group and the groups can be formed by frames.