Abstract: Apparatus and methods to determine in-aisle locations in monitored environments are disclosed. An example apparatus includes first and second sensors in communication with a location meter. The first sensor is to detect (1) a first sequence of position indicators when the location meter is moving along an aisle of a monitored environment in a first direction, or (2) a second sequence of the position indicators when the location meter is moving along the aisle in a second direction opposite the first direction. The second sensor is to detect (1) the second sequence of position indicators when the location meter is moving along the aisle in the first direction, or (2) the first sequence of the position indicators when the location meter is moving along the aisle in the second direction. An in-aisle position of the location meter is to be determined based on the first and second sequences of position indicators.

Abstract: Example methods and apparatus for auditing signage are disclosed. A disclosed example method involves directing an operator to a signage location and capturing an image of a signage at the signage location. The example method also includes detecting an actual characteristic of the signage based on the image and comparing the actual characteristic to an expected characteristic.

Abstract: Example methods and apparatus for auditing signage are disclosed. A disclosed example method involves directing an operator to a signage location and capturing an image of a signage at the signage location. The example method also includes detecting an actual characteristic of the signage based on the image and comparing the actual characteristic to an expected characteristic.

Abstract: Example methods and apparatus for auditing signage are disclosed. A disclosed example method involves directing an operator to a signage location and capturing an image of a signage at the signage location. The example method also includes detecting an actual characteristic of the signage based on the image and comparing the actual characteristic to an expected characteristic.

Abstract: Methods and apparatus for metering printed media are disclosed. A disclosed example apparatus comprises a first radio frequency identification (RFID) tag to adhere to a first leaflet of a printed media at a first location; a second RFID tag to adhere to a second leaflet of the printed media at a second location of the second leaflet, the first and second locations being substantially a same location; and a first RFID absorber to adhere to a third leaflet of the printed media such that, when the printed media is positioned to expose the first and the third leaflets, the second RFID tag is inactive, and such that, when the printed media is positioned to expose the second and the third leaflets, the first RFID tag is inactive.

Abstract: The present invention provides for a method for a load address dependency mechanism in a high frequency, low power processor. A load instruction corresponding to a memory address is received. At least one unexecuted preceding instruction corresponding to the memory address is identified. The load instruction is stored in a miss queue. And the load instruction is tagged as a local miss.

Abstract: Example methods and apparatus for auditing signage are disclosed. A disclosed example method involves directing an operator to a signage location and capturing an image of a signage at the signage location. The example method also includes detecting an actual characteristic of the signage based on the image and comparing the actual characteristic to an expected characteristic.

Abstract: Methods and apparatus for metering printed media are disclosed. A disclosed example apparatus comprises a first radio frequency identification (RFID) tag to adhere to a first leaflet of a printed media at a first location; a second RFID tag to adhere to a second leaflet of the printed media at a second location of the second leaflet, the first and second locations being substantially a same location; and a first RFID absorber to adhere to a third leaflet of the printed media such that, when the printed media is positioned to expose the first and the third leaflets, the second RFID tag is inactive, and such that, when the printed media is positioned to expose the second and the third leaflets, the first RFID tag is inactive.

Abstract: Methods and apparatus to survey a retail environment are disclosed herein. A disclosed example method involves moving a cart in a retail establishment having a camera. The method also involves capturing a first image of a first area and a second image of a second area. A stitched image is generated based on the first and second images. The stitched image is associated with product codes based on products appearing in the stitched image.

Abstract: A method, an apparatus, and a computer program product are provided for detecting load/store dependency in a memory system by dynamically changing the address width for comparison. An incoming load/store operation must be compared to the operations in the pipeline and the queues to avoid address conflicts. Overall, the present invention introduces a cache hit or cache miss input into the load/store dependency logic. If the incoming load operation is a cache hit, then the quadword boundary address value is used for detection. If the incoming load operation is a cache miss, then the cacheline boundary address value is used for detection. This invention enhances the performance of LHS and LHR operations in a memory system.

Abstract: Example methods and apparatus for collecting media site data for use with media exposure measurement systems are disclosed. A disclosed example method involves displaying a first image of a scene and receiving a user-provided selection of a location in the first image. An object of interest in the scene is then identified based on the user-provided selection in the first image. The example method also involves obtaining a distance value representative of an approximate distance between an image capturing device and the object of interest in the scene. A zoom level of the image capturing device is then set based on the distance value to capture at least a portion of the object of interest in the scene. A second image of the object of interest is captured using the image capturing device.

Abstract: The present invention provides for a method for a load address dependency mechanism in a high frequency, low power processor. A load instruction corresponding to a memory address is received. At least one unexecuted preceding instruction corresponding to the memory address is identified. The load instruction is stored in a miss queue. And the load instruction is tagged as a local miss.

Abstract: The present invention provides for a method for a load address dependency mechanism in a high frequency, low power processor. A load instruction corresponding to a memory address is received. At least one unexecuted preceding instruction corresponding to the memory address is identified. The load instruction is stored in a miss queue. And the load instruction is tagged as a local miss.

Abstract: The present invention provides a method of updating the cache state information for store transactions in an system in which store transactions only read the cache state information upon entering the unit pipe or store portion of the store/load queue. In this invention, store transactions in the unit pipe and queue are checked whenever a cache line is modified, and their cache state information updated as necessary. When the modification is an invalidate, the check tests that the two share the same physical addressable location. When the modification is a validate, the check tests that the two involve the same data cache line.

Abstract: A method of retiring operations to a cache. Initially, a first operation is queued in a stack such as the store queue of a retire unit. The first operation is then copied, in a first transfer, to a latch referred to as the miss latch in response to a resource conflict that prevents the first operation from accessing the cache. The first operation is maintained in the stack for the duration of the resource conflict. When the resource conflict is resolved, the cache is accessed, in a first cache access, with the first operation from the stack. Preferably, the first operation is removed from the stack when the resource conflict is resolved and the first cache access is initiated. In the preferred embodiment, the first operation is maintained in the miss latch until the first cache access results in a cache hit.

Abstract: A deallocation pipelining circuit for use in a cache memory subsystem. The pipelining circuit is configured to initiate a storeback buffer (SBB) transfer of first line data stored in a first line of a cache memory array if the deallocation pipelining circuit detects a cache miss signal corresponding to the first line and identifies the first line data as modified data. The deallocation pipelining circuit is configured to issue a storeback request signal to a bus interface unit after the completion of the SBB transfer. The circuit initiates a bus interface unit transfer of the first line data after receiving a data acknowledge signal from the bus interface unit. The pipelining circuit is still further configured to deallocate the first line of the cache memory after receiving a request acknowledge signal from the bus interface unit.

Abstract: A cache has an array for holding data or instruction values, a buffer connected to the array, and means for accessing the buffer to retrieve a value for a processing unit. The accessing means uses wires having a pitch which is substantially equal to a wire pitch of the cache array. Multiplexers can be used with a plurality of such buffers to create a common output path. The cache can be interleaved, with the array being a first subarray, and the buffer being a first buffer, and further comprising a second subarray and a second buffer, wherein the first and second buffers separate the first and second subarrays. The invention can be applied to a store-back buffer as well as a reload buffer.

Abstract: An interleaved data cache array which is divided into two subarrays is provided for utilization within a data processing system. Each subarray includes a plurality of cache lines wherein each cache line includes a selected block of data, a parity field, a content addressable field containing a portion of an effective address (ECAM) for the selected block of data, a second content addressable field contains a real address (RCAM) for the selected block of data and a data status field. Separate effective address ports (EA) and a real address port (RA) permit parallel access to the cache without conflict in separate subarrays and a subarray arbitration logic circuit is provided for attempted simultaneous access of a single subarray by both the effective address port (EA) and the real address port (RA). A normal word line is provided and activated by either the effective address port or the real address port through the subarray arbitration.

Abstract: Within a data processing system implementing primary and secondary caches and stream filters and buffers, prefetching of cache lines is performed in a progressive manner. In one mode, data may not be prefetched. In a second mode, two cache lines are prefetched wherein one line is prefetched into the L1 cache and the next line is prefetched into a stream buffer. In a third mode, more than two cache lines are prefetched at a time. Prefetching may be performed on cache misses or hits. Cache misses on successive cache lines may allocate a stream of cache lines to the stream buffers. Control circuitry, coupled to a stream filter circuit, selectively controls fetching and prefetching of data from system memory to the primary and secondary caches associated with a processor and to a stream buffer circuit.

Abstract: A method and apparatus for identifying data that contains an uncorrectable error may be accomplished in a computer that includes a memory unit operably coupled to a processor. The memory unit includes an error detection circuit that, when an uncorrectable storage error is detected, produces transmit check bits indicating that the data being transmitted includes an uncorrectable storage error. The processor, which includes a check bit decoder, upon receiving the transmit check bits, interprets the transmit check bits to identify the uncorrectable error. When the uncorrectable error is identified, the check bit decoder provides a data error signal to a processing core of the processor, thereby interrupting the processing core which avoids a system error and the need to reboot the computer.