Abstract: A processing device comprising: at least one execution unit configured to interleave execution of a plurality of worker threads, wherein each of the worker threads is configured to execute a same set of code to perform operations on a different set of data held in an input buffer of a memory of the processing device and output the results data to an output buffer. An instruction is executed so as to cause a plurality of operand registers, each of which is associated with one of the worker threads, to be populated with one or more variables enabling each worker to determine where in the input buffer is located its set of input data and where to store its results data.

Abstract: By providing a mode indication, an execution unit is operable to operate in two separate modes, each of which cause the execution unit to perform calculations by interpreting the same bit string (the first of the bit strings) as representing one of two different values. When operating in the first mode, the first of the bit string represents an undefined value, in other words a NaN. When operating in the second mode, the first of the bit strings represents a negative zero. Hence, the same string of bits can represent either a NaN or a negative zero depending upon the mode of operation of the processor. Since it is not necessary to reserve more than one bit string to represent these two special values, the remaining combinations of bits are available to represent other values.

Abstract: A processing device comprises a register configured to store a count value indicating a number of times overflow events have resulted from arithmetic operations performed by the processing device. An execution unit of the device, in response to performing an arithmetic operation having a result which extends beyond one of the predefined limit values for the floating-point format, stores a result value that is within the predefined limit values, and cause the count value to be incremented. The count value provides a performant way of determining the number of overflow events that have occurred during the arithmetic processing performed by the execution unit. The count value provides a metric that provides a measure of the inaccuracy imparted into the results of the application processing by overflow events.

Abstract: A hardware module is provided in an execution unit and is responsive to execution of multiple instances of a new type of instruction to perform a plurality of reductions in parallel. The hardware module comprises: a first accumulator storing first state associated with a first of the reductions; and a second accumulator storing second state associated with a second of the reductions. Upon execution of each of the multiple instances of the first type of instruction: an input value for the respective instance is provided to a first processing circuit of the hardware module such that the first processing circuit performs a first type of operation to update the first state; and the same input value is provided to the second processing circuit of the hardware module such that the second processing circuit performs a second type of operation to update the second state.

Abstract: A processing device comprising: a control register configured to store a scaling factor; at least one execution unit configured to execute instructions to perform arithmetic operations on input floating-point numbers provided according to a first floating-point format, wherein each of the input floating-point numbers provided according to the first floating-point format comprises a predetermined number of bits, wherein the at least one execution unit is configured to, in response to execution of an instance of a first of the instructions: perform processing of a first set of the input floating-point numbers to generate a result value, the result value provided in a further format and comprising more the predetermined number of bits, enabling representation of a greater range of values than is representable in the first floating-point format; and apply the scaling factor specified in the control register to increase or decrease an exponent of the result value.

Abstract: A new type of instruction and a control register for the new type of instruction are provided to handle data that may be misaligned in memory. A first part of data (which may be misaligned in memory) is loaded into a first set of registers by loading a first atom containing the first part of data into registers. The pack instruction is executed by an execution unit to place part of data (whose length and starting position are indicated by second and third values in a control register) from one set of registers into an identified location (identified by a first value in the control register) in another set of registers.

Abstract: A processing device comprising a plurality of operand registers, wherein a first subset of the operand registers are configured to store state information for a plurality of bins, comprising a range of values and a bin count associated with each respective bin, wherein a second subset of the operand registers is configured to store a vector of floating-point values; and an execution unit configured to execute a first instruction taking the state information for the plurality of bins and the vector of floating-point values as operands, and in response to execution of the first instruction, for each of the floating-point values: identify based on an exponent of the respective floating-point value, each one of the plurality of bins for which the respective floating-point value falls within the associated range of values; and increment the bin count associated with the identified bins.

Abstract: A processor comprising: a register file comprising a group of operand registers for holding data values, each operand register being a fixed number of bits in length for holding a respective data value of that length; and processing logic comprising floating point logic for performing floating point operations on data values in the register file, the floating point logic is configured to process the fixed number of bits in the respective data value according to a floating point format comprising a set of mantissa bits and a set of exponent bits. The processing logic is operable to select between a plurality of different variants of the floating point format, at least some of the variants having a different size sets of mantissa bits and exponent bits relative to one another.

Abstract: A processing device comprises a register configured to store a count value indicating a number of times overflow events have resulted from arithmetic operations performed by the processing device. An execution unit of the device, in response to performing an arithmetic operation having a result which extends beyond one of the predefined limit values for the floating-point format, stores a result value that is within the predefined limit values, and cause the count value to be incremented. The count value provides a performant way of determining the number of overflow events that have occurred during the arithmetic processing performed by the execution unit. The count value provides a metric that provides a measure of the inaccuracy imparted into the results of the application processing by overflow events.

Abstract: A multi-tile processing unit in which the tiles in the processing unit may be divided between two or more different external sync groups for performing barrier synchronisations. In this way, different sets of tiles of the same processing unit each sync with different sets of tiles external to that processing unit.

Abstract: A processing device comprising a plurality of operand registers, wherein a first subset of the operand registers are configured to store state information for a plurality of bins, comprising a range of values and a bin count associated with each respective bin, wherein a second subset of the operand registers is configured to store a vector of floating-point values; and an execution unit configured to execute a first instruction taking the state information for the plurality of bins and the vector of floating-point values as operands, and in response to execution of the first instruction, for each of the floating-point values: identify based on an exponent of the respective floating-point value, each one of the plurality of bins for which the respective floating-point value falls within the associated range of values; and increment the bin count associated with the identified bins.

Abstract: A processing device comprising: a control register configured to store a scaling factor; at least one execution unit configured to execute instructions to perform arithmetic operations on input floating-point numbers provided according to a first floating-point format, wherein each of the input floating-point numbers provided according to the first floating-point format comprises a predetermined number of bits, wherein the at least one execution unit is configured to, in response to execution of an instance of a first of the instructions: perform processing of a first set of the input floating-point numbers to generate a result value, the result value provided in a further format and comprising more the predetermined number of bits, enabling representation of a greater range of values than is representable in the first floating-point format; and apply the scaling factor specified in the control register to increase or decrease an exponent of the result value.

Abstract: A hardware module is provided in an execution unit and is responsive to execution of multiple instances of a new type of instruction to perform a plurality of reductions in parallel. The hardware module comprises: a first accumulator storing first state associated with a first of the reductions; and a second accumulator storing second state associated with a second of the reductions. Upon execution of each of the multiple instances of the first type of instruction: an input value for the respective instance is provided to a first processing circuit of the hardware module such that the first processing circuit performs a first type of operation to update the first state; and the same input value is provided to the second processing circuit of the hardware module such that the second processing circuit performs a second type of operation to update the second state.

Abstract: By providing a mode indication, an execution unit is operable to operate in two separate modes, each of which cause the execution unit to perform calculations by interpreting the same bit string (the first of the bit strings) as representing one of two different values. When operating in the first mode, the first of the bit string represents an undefined value, in other words a NaN. When operating in the second mode, the first of the bit strings represents a negative zero. Hence, the same string of bits can represent either a NaN or a negative zero depending upon the mode of operation of the processor. Since it is not necessary to reserve more than one bit string to represent these two special values, the remaining combinations of bits are available to represent other values.

Abstract: A processing device comprising: at least one execution unit configured to interleave execution of a plurality of worker threads, wherein each of the worker threads is configured to execute a same set of code to perform operations on a different set of data held in an input buffer of a memory of the processing device and output the results data to an output buffer. An instruction is executed so as to cause a plurality of operand registers, each of which is associated with one of the worker threads, to be populated with one or more variables enabling each worker to determine where in the input buffer is located its set of input data and where to store its results data.

Abstract: A new type of instruction and a control register for the new type of instruction are provided to handle data that may be misaligned in memory. A first part of data (which may be misaligned in memory) is loaded into a first set of registers by loading a first atom containing the first part of data into registers. The pack instruction is executed by an execution unit to place part of data (whose length and starting position are indicated by second and third values in a control register) from one set of registers into an identified location (identified by a first value in the control register) in another set of registers.

Abstract: A multi-tile processing unit in which the tiles in the processing unit may be divided between two or more different external sync groups for performing barrier synchronisations. In this way, different sets of tiles of the same processing unit each sync with different sets of tiles external to that processing unit.

Abstract: A processor comprising: a register file comprising a group of operand registers for holding data values, each operand register being a fixed number of bits in length for holding a respective data value of that length; and processing logic comprising floating point logic for performing floating point operations on data values in the register file, the floating point logic is configured to process the fixed number of bits in the respective data value according to a floating point format comprising a set of mantissa bits and a set of exponent bits. The processing logic is operable to select between a plurality of different variants of the floating point format, at least some of the variants having a different size sets of mantissa bits and exponent bits relative to one another.

Abstract: Disclosed herein is a method of optimizing an executable program to improve instruction cache hit rate when executed on a processor. A method of predicting instruction cache behavior of an executable program is also disclosed. According to further aspects of the present invention, there is provided a software development tool product comprising code which when executed on a computer will perform the method of optimizing an executable program. A linker product and a computer program are also disclosed.

Abstract: A method, chip and computer program product for booting from a secondary boot source. In one embodiment, the method includes: (1) retrieving primary boot code from an on-chip primary boot source on the same chip as a processor, the primary boot code comprising at least a boot discovery algorithm for determining the location of an external secondary boot source external to said chip, (2) executing the primary boot code on the processor, including the boot discovery algorithm, thus operating the processor to check each of a plurality of locations to determine the location of the external secondary boot source, (3) retrieving the secondary boot code from the determined location and (4) continuing the booting of the processor by executing the secondary boot code on the processor.