Abstract: Apparatus and methods for detecting and identifying a cause of a hot-switching event in an automated test system. One or more antennae positioned near mechanical relays in the system may be used to sense electromagnetic radiation. The antennae may be configured to respond to electromagnetic radiation of the type generated during a hot-switching event. Signals measured by the antennae may be processed to determine whether the signals have characteristics of hot-switching events. Processing may entail generating a signal envelope and determining whether the envelope has characteristics indicative of a hot-switching event. When a hot-switching event is detected, information to correlate the event to other events in the test system may also be captured. That information may be time information, enabling program test-system program instructions executing at the time of the event to be identified, such that the test system may be reprogrammed to avoid hot-switching events.

Abstract: Apparatus and methods for detecting and identifying a cause of a hot-switching event in an automated test system. One or more antennae positioned near mechanical relays in the system may be used to sense electromagnetic radiation. The antennae may be configured to respond to electromagnetic radiation of the type generated during a hot-switching event. Signals measured by the antennae may be processed to determine whether the signals have characteristics of hot-switching events. Processing may entail generating a signal envelope and determining whether the envelope has characteristics indicative of a hot-switching event. When a hot-switching event is detected, information to correlate the event to other events in the test system may also be captured. That information may be time information, enabling program test-system program instructions executing at the time of the event to be identified, such that the test system may be reprogrammed to avoid hot-switching events.

Abstract: A high-speed tester channel architecture is disclosed for delivering and receiving signals to and from a device-under-test. The tester channel architecture includes drive/compare circuitry having respective driver and comparator transmission line paths and backmatch resistor circuitry to establish a backmatch condition. Peaking circuitry is disposed in each of the driver and comparator transmission line paths. The peaking circuitry includes a capacitive branch and an inductive branch operative to preserve the backmatch condition.

Abstract: An improved ATE and methods are provided by forming and comparing pattern bursts digitally in gallium arsenide IC's. A desired burst waveform at the DUT terminal is facilitated by setting into timing generators between bursts in effect a plurality of period waveforms constituting a palate from which by successive choice the DUT-terminal driver and comparator waveforms may be built up, each period driver waveform including a predetermined number (including zero) of rising or falling edges, any particular such edge in any particular period driver waveform being provided by the timing generators and each period comparator waveforms including voltage levels to be compared and edges provided through the timing generators, the timing generators being settable only between bursts, selection of desired palette waveforms being provided for each period by a pattern memory.