Patents by Inventor Alan Benner

Alan Benner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9606303
    Abstract: A tool-less grouping apparatus has a main body with a top portion and a bottom portion. Dividing members extending between the top and bottom portions make openings for fiber optic connectors. Forward facing surfaces may be on both the top and bottom portions to engage the fiber optic connectors. The portions also have cut-outs that can engage the fiber optic connectors to assist in removing the fiber optic connectors from adapters.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: March 28, 2017
    Assignees: US Conec, Ltd., International Business Machines Corporation
    Inventors: Jillcha F. Wakjira, Alan Benner, Russell Granger, Darrell R. Childers
  • Patent number: 8811378
    Abstract: A computing system includes: a plurality of tightly coupled processing nodes; a plurality of circuit switched networks using a circuit switching mode, interconnecting the processing nodes, and handling data transfers that meet one or more criteria; and a plurality of electronic packet switched networks, also interconnecting the processing nodes, handling data transfers that do meet the at least one criteria. The circuit switched networks and the electronic packet switched networks operate simultaneously.
    Type: Grant
    Filed: April 11, 2012
    Date of Patent: August 19, 2014
    Assignee: International Business Machines Corporation
    Inventors: Alan Benner, Ramakrishnan Rajamony, Eugen Schenfeld, Craig Brian Stunkel, Peter A. Walker
  • Patent number: 8644327
    Abstract: A switching device is able to route the arriving data packets according to data packet destination information to dedicated output ports. The switching arrangement has, for each set of input ports in the switching device, a set of output buffers with an output buffer for storing the payload of each data packet at an address in the output buffer which pertains to the same set of output buffers and belongs to the dedicated output ports. At least one of the output buffers has a set of output queues with an output queue for each output port for storing the address of each payload stored in the corresponding output buffer. An arbiter controls a readout order of the stored addresses. For the output buffers which pertain to the same set of output ports a multiplexer multiplexes according to the readout order the payloads from the output buffers to the output ports.
    Type: Grant
    Filed: November 17, 2010
    Date of Patent: February 4, 2014
    Assignee: International Business Machines Corporation
    Inventors: Alan Benner, Antonius Engberson, Gottfried Goldrian, Ronald Luijten
  • Patent number: 8559781
    Abstract: A sleeve has a handle and extensions to engage a fiber optic connector for insertion into and removal from high density adapters. The sleeve may have multiple connectors installed in a single sleeve and it may be removable. The sleeve has first and second extensions to engage the inner and outer housings, respectively, to insert and remove the fiber optic connector from an adapter.
    Type: Grant
    Filed: November 6, 2009
    Date of Patent: October 15, 2013
    Assignee: US Conec, Ltd.
    Inventors: Darrell R. Childers, Myron Yount, Russell Granger, Joe Howard, Alan Benner, Robert K. Mullady
  • Publication number: 20120251051
    Abstract: A tool-less grouping apparatus has a main body with a top portion and a bottom portion. Dividing members extending between the top and bottom portions make openings for fiber optic connectors. Forward facing surfaces may be on both the top and bottom portions to engage the fiber optic connectors. The portions also have cut-outs that can engage the fiber optic connectors to assist in removing the fiber optic connectors from adapters.
    Type: Application
    Filed: March 1, 2012
    Publication date: October 4, 2012
    Inventors: Jillcha F. Wakjira, Alan Benner, Russell Granger, Darrell R. Childers
  • Publication number: 20120195591
    Abstract: A computing system includes: a plurality of tightly coupled processing nodes; a plurality of circuit switched networks using a circuit switching mode, interconnecting the processing nodes, and handling data transfers that meet one or more criteria; and a plurality of electronic packet switched networks, also interconnecting the processing nodes, handling data transfers that do meet the at least one criteria. The circuit switched networks and the electronic packet switched networks operate simultaneously.
    Type: Application
    Filed: April 11, 2012
    Publication date: August 2, 2012
    Applicant: International Business Machines Corporation
    Inventors: Alan Benner, Ramakrishnan Rajamony, Eugen Schenfeld, Craig Brian Stunkel, Peter A. Walker
  • Patent number: 8194638
    Abstract: Briefly, according to an embodiment of the invention, a computing system comprises: a plurality of tightly coupled processing nodes; a plurality of circuit switched networks using a circuit switching mode, interconnecting the processing nodes, and for handling data transfers that meet one or more criteria; and a plurality of electronic packet switched networks, also interconnecting the processing nodes, for handling data transfers that do meet the at least one criteria. The circuit switched networks and the electronic packet switched networks operate simultaneously. The system additionally comprises a plurality of clusters which comprise the processing nodes, and a plurality of intra-cluster communication links. The electronic packet switched networks are for handling collectives and short-lived data transfers among the processing nodes and comprises one-tenth of the bandwidth of the circuit switched networks.
    Type: Grant
    Filed: July 27, 2006
    Date of Patent: June 5, 2012
    Assignee: International Business Machines Corporation
    Inventors: Alan Benner, Ramakrishnan Rajamony, Eugen Schenfeld, Craig Brian Stunkel, Peter A. Walker
  • Patent number: 8009702
    Abstract: A communication system which consists of several modules—operating in parallel on segments of a packet—to increase speed and handling capacity. One module acts as master, the others are slave modules controlled by control signals derived by the master module. It is important that in each module the data segment and the respective control signal of each packet are correctly synchronized, because in large systems the data paths carrying packet segments and the control signal paths may have substantially different delays. The invention provides for measurement of the propagation delay differences and for introducing a controlled delay in each slave module, so that data segments and control signals can be correctly correlated by delaying either the one or the other. Synchronization packets are transmitted besides normal data packets, for obtaining time stamps which are used to determine the delay difference.
    Type: Grant
    Filed: May 11, 2010
    Date of Patent: August 30, 2011
    Assignee: International Business Machines Corporation
    Inventors: Michel Colmant, Alan Benner, Francois G. Abel, Michel Poret, Norbert Schumacher, Alain Blanc, Mark Verhappen, Mitch Gusat
  • Publication number: 20110149729
    Abstract: A switching device is able to route the arriving data packets according to data packet destination information to dedicated output ports. The switching arrangement has, for each set of input ports in the switching device, a set of output buffers with an output buffer for storing the payload of each data packet at an address in the output buffer which pertains to the same set of output buffers and belongs to the dedicated output ports. At least one of the output buffers has a set of output queues with an output queue for each output port for storing the address of each payload stored in the corresponding output buffer. An arbiter controls a readout order of the stored addresses. For the output buffers which pertain to the same set of output ports a multiplexer multiplexes according to the readout order the payloads from the output buffers to the output ports.
    Type: Application
    Filed: November 17, 2010
    Publication date: June 23, 2011
    Applicant: International Business Machines Corporation
    Inventors: Alan Benner, Antonius Engberson, Gottfried Goldrian, Ronald Luijten
  • Publication number: 20110019962
    Abstract: A sleeve has a handle and extensions to engage a fiber optic connector for insertion into and removal from high density adapters. The sleeve may have multiple connectors installed in a single sleeve and it may be removable. The sleeve has first and second extensions to engage the inner and outer housings, respectively, to insert and remove the fiber optic connector from an adapter.
    Type: Application
    Filed: November 6, 2009
    Publication date: January 27, 2011
    Inventors: Darrell R. Childers, Myron Yount, Russell Granger, Joe Howard, Alan Benner, Robert K. Mullady
  • Patent number: 7848341
    Abstract: Discloses a switching arrangement for packets of data, with several input ports and several output ports and which is determined for the transportation of incoming packets to one or more designated of the output ports and from there to a subsequent device. More particularly it relates to a switching arrangement and method wherein for each input port a set of output buffers is arranged, each set comprising an output buffer for each output port.
    Type: Grant
    Filed: February 25, 2002
    Date of Patent: December 7, 2010
    Assignee: International Business Machines Corporation
    Inventors: Alan Benner, Antonius Engbersen, Gottfried Goldrian, Ronald Luijten
  • Publication number: 20100220749
    Abstract: A communication system which consists of several modules—operating in parallel on segments of a packet—to increase speed and handling capacity. One module acts as master, the others are slave modules controlled by control signals derived by the master module. It is important that in each module the data segment and the respective control signal of each packet are correctly synchronized, because in large systems the data paths carrying packet segments and the control signal paths may have substantially different delays. The invention provides for measurement of the propagation delay differences and for introducing a controlled delay in each slave module, so that data segments and control signals can be correctly correlated by delaying either the one or the other. Synchronization packets are transmitted besides normal data packets, for obtaining time stamps which are used to determine the delay difference.
    Type: Application
    Filed: May 11, 2010
    Publication date: September 2, 2010
    Applicant: International Business Machines Corporation
    Inventors: Michael COLMANT, Alan Benner, Francois G. Abel, Michel Poret, Norbert Schumacher, Alain Blanc, Mark Verhappen, Mitch Gusat
  • Patent number: 7720105
    Abstract: For switching or transmitting data packets, one can provide communication systems which consist of several modules —operating in parallel on segments of a packet —to increase speed and handling capacity. One module acts as master, others are slave modules controlled by control signals derived by the master module. It is important to correctly synchronize in each module the data segment and the respective control signal of each packet, because in large systems the data paths carrying packet segments and the control signal paths may have substantially different delays. The invention provides for measurement of the propagation delay differences and for introducing a controlled delay in each slave module, so that data segments and control signals can be correctly correlated by delaying either the one or the other. Synchronization packets are transmitted besides normal data packets, for obtaining time stamps which are used to determine the delay difference.
    Type: Grant
    Filed: March 31, 2003
    Date of Patent: May 18, 2010
    Assignee: International Business Machines Corporation
    Inventors: Michael Colmant, Alan Benner, Francois G. Abel, Michel Poret, Norbert Schumacher, Alain Blanc, Mark Verhappen, Mitch Gusat
  • Publication number: 20080089322
    Abstract: A computer readable storage medium includes instructions that, when executed by a computer, implement a method for delay optimization scheduling in bufferless crossbar switches, the method including: transmitting, by each line card of a plurality of line cards logically organized into rows and columns, scheduling information to a horizontal control broadcast network and a vertical control broadcast network; receiving, by each line card, a plurality of requests from the horizontal and the vertical control broadcast networks connected to that line card, the requests being from the other line cards in a same row and a same column as that line card; performing, by each line card, a two-phase distribution of the requests; determining, by each line card, a partial schedule for that line card based on the scheduling information and the requests; and sending, by each line card, data according to the partial schedule through a bufferless crossbar switch.
    Type: Application
    Filed: November 30, 2007
    Publication date: April 17, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Alan Benner, Casimer DeCusatis
  • Patent number: 7359318
    Abstract: A method and systems for dynamically distributing packet flows over multiple network processing means and recombining packet flows after processing while keeping packet order even for traffic wherein an individual flow exceeds the performance capabilities of a single network processing means is disclosed. After incoming packets have been analyzed to identify the flow the packets are parts of, the sequenced load balancer of the invention dynamically distributes packets to the connected independent network processors. A balance history is created per flow and updated each time a packet of the flow is received and/or transmitted. Each balance history memorizes, in time order, the identifier of network processor having handled packets of the flow and the associated number of processed packets. Processed packets are then transmitted back to a high-speed link or memorized to be transmitted back to the high-speed link later, depending upon the current status of the balance history.
    Type: Grant
    Filed: February 27, 2003
    Date of Patent: April 15, 2008
    Assignee: International Business Machines Corporation
    Inventors: Francois Abel, Alan Benner, Gero Dittmann, Andreas Herkersdorf
  • Publication number: 20080069109
    Abstract: A system for delay optimization scheduling in bufferless crossbar switches includes a plurality of line cards, each line card having an ingress half, an egress half, and a partial scheduler, wherein each line card is configured to transmit scheduling information to a horizontal control broadcast network and a vertical control broadcast network; a plurality of couplers connected by control links to the line cards in a two-dimensional grid, organizing the line cards into rows and columns; a bufferless crossbar switch connected by data path links to each line card to the ingress half and the egress half; wherein control information is distributed in a first stage and a second stage of broadcasts.
    Type: Application
    Filed: November 30, 2007
    Publication date: March 20, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Alan Benner, Casimer DeCusatis
  • Publication number: 20080025288
    Abstract: Briefly, according to an embodiment of the invention, a computing system comprises: a plurality of tightly coupled processing nodes; a plurality of circuit switched networks using a circuit switching mode, interconnecting the processing nodes, and for handling data transfers that meet one or more criteria; and a plurality of electronic packet switched networks, also interconnecting the processing nodes, for handling data transfers that do meet the at least one criteria. The circuit switched networks and the electronic packet switched networks operate simultaneously. The system additionally comprises a plurality of clusters which comprise the processing nodes, and a plurality of intra-cluster communication links. The electronic packet switched networks are for handling collectives and short-lived data transfers among the processing nodes and comprises one-tenth of the bandwidth of the circuit switched networks.
    Type: Application
    Filed: July 27, 2006
    Publication date: January 31, 2008
    Inventors: Alan Benner, Ramakrishnan Rajamony, Eugen Schenfeld, Craig Brian Stunkel, Peter A. Walker
  • Publication number: 20070110087
    Abstract: A method and system for reducing arbitration latency employs speculative transmission (STX) without prior arbitration in combination with routing fabric scheduled arbitration. Packets are sent from source locations to a routing fabric through scheduled arbitration, and also through speculative arbitration, to non-contentiously allocate outputs that were not previously reserved in the routing fabric to the speculatively transmitted packets.
    Type: Application
    Filed: April 10, 2006
    Publication date: May 17, 2007
    Inventors: Francois Abel, Alan Benner, Richard Grzybowski, Brewster Hemenway, Ilias Iliadis, Rajaram Krishnamurthy, Ronald Luijten, Cyriel Minkenberg
  • Publication number: 20060251124
    Abstract: For switching or transmitting data packets, one can provide communication systems which consist of several modules—operating in parallel on segments of a packet—to increase speed and handling capacity. One module acts as master (21), the others are slave modules (22) controlled by control signals (25) derived by the master module. It is important that in each module the data segment and the respective control signal of each packet are correctly synchronized, because in large systems the data paths carrying packet segments and the control signal paths may have substantially different delays. The invention provides for measurement of the propagation delay differences and for introducing a controlled delay in each slave module, so that data segments and control signals can be correctly correlated by delaying either the one or the other. Synchronization packets are transmitted besides normal data packets, for obtaining time stamps which are used to determine the delay difference.
    Type: Application
    Filed: March 31, 2003
    Publication date: November 9, 2006
    Inventors: Michel Colmant, Alan Benner, Francois Abel, Michel Poret, Norhert Schumacher, Alain Blanc, Mark Verhappen, Mitch Gusat
  • Publication number: 20060221948
    Abstract: The interconnecting network for switching data packets, having data and flow control information, comprises a local packet switch element (S1) with local input buffers (I(1,1) . . . I(1,y)) for buffering the incoming data packets, a remote packet switch element (S2) with remote input buffers (I(2,1) . . . I(2,y)) for buffering the incoming data packets, and data lines (L) for interconnecting the local and the remote packet switch elements (S1, S2). The interconnecting network further comprises a local and a remote arbiter (A1, A2) which are connected via control lines (CL) to the input buffers (I(1,1) . . . I(1,y), I(2,1) . . . I(2,y)), and which are formed such that they can provide that the flow control information is transmitted via the data lines (L) and the control lines (CL).
    Type: Application
    Filed: March 31, 2005
    Publication date: October 5, 2006
    Applicant: International Business Machines Corporation
    Inventors: Alan Benner, Cyriel Minkenberg, Craig Stunkel