Abstract: Methods form transistor structures that include, among other components, a substrate having an active region bordered by an isolation region, a gate insulator on the substrate, and a gate conductor on the gate insulator. First and second sections of the gate conductor are within the active region of the substrate, while a third section is in the isolation region of the substrate. The second section of the gate conductor tapers from the width of the first section to the width of the wider third section. The first section and the second section of the gate conductor have undercut regions where the corner of the gate conductor contacts the substrate. The third section of the gate conductor lacks the undercut regions. The gate insulator is relatively thicker in the undercut regions and is relatively thinner where the corner of the gate conductor lacks the undercut regions in the isolation region.

Abstract: Methods form transistor structures that include, among other components, a substrate having an active region bordered by an isolation region, a gate insulator on the substrate, and a gate conductor on the gate insulator. First and second sections of the gate conductor are within the active region of the substrate, while a third section is in the isolation region of the substrate. The second section of the gate conductor tapers from the width of the first section to the width of the wider third section. The first section and the second section of the gate conductor have undercut regions where the corner of the gate conductor contacts the substrate. The third section of the gate conductor lacks the undercut regions. The gate insulator is relatively thicker in the undercut regions and is relatively thinner where the corner of the gate conductor lacks the undercut regions in the isolation region.

Abstract: Methods form transistor structures that include, among other components, a substrate having an active region bordered by an isolation region, a gate insulator on the substrate, and a gate conductor on the gate insulator. First and second sections of the gate conductor are within the active region of the substrate, while a third section is in the isolation region of the substrate. The second section of the gate conductor tapers from the width of the first section to the width of the wider third section. The first section and the second section of the gate conductor have undercut regions where the corner of the gate conductor contacts the substrate. The third section of the gate conductor lacks the undercut regions. The gate insulator is relatively thicker in the undercut regions and is relatively thinner where the corner of the gate conductor lacks the undercut regions in the isolation region.

Abstract: A structure, and a method for forming the same. The structure includes a semiconductor substrate which includes a top substrate surface, a buried dielectric layer on the top substrate surface, N active semiconductor regions on the buried dielectric layer, N active devices on the N active semiconductor regions, a plurality of dummy regions on the buried dielectric layer, a protection layer on the N active devices and the N active semiconductor regions, but not on the plurality of dummy regions. The N active devices comprise first active regions which comprise a first material. The plurality of dummy regions comprise first dummy regions which comprise the first material. A first pattern density of the first active regions and the first dummy regions is uniform across the structure. A trench in the buried dielectric layer such that side walls of the trench are aligned with the plurality of dummy regions.

Abstract: Methods and structures for improving substrate loss and linearity in SOI substrates. The methods include forming damaged crystal structure regions under the buried oxide layer of SOI substrates and the structures included damaged crystal structure regions under the buried oxide layer of the SOI substrate.

Abstract: Methods and structures for improving substrate loss and linearity in SOI substrates. The methods include forming damaged crystal structure regions under the buried oxide layer of SOI substrates and the structures included damaged crystal structure regions under the buried oxide layer of the SOI substrate.

Abstract: A structure, and a method for forming the same. The structure includes a semiconductor substrate which includes a top substrate surface, a buried dielectric layer on the top substrate surface, N active semiconductor regions on the buried dielectric layer, N active devices on the N active semiconductor regions, a plurality of dummy regions on the buried dielectric layer, a protection layer on the N active devices and the N active semiconductor regions, but not on the plurality of dummy regions. The N active devices comprise first active regions which comprise a first material. The plurality of dummy regions comprise first dummy regions which comprise the first material. A first pattern density of the first active regions and the first dummy regions is uniform across the structure. A trench in the buried dielectric layer such that side walls of the trench are aligned with the plurality of dummy regions.

Abstract: An electrical structure and method of forming. The method includes providing a semiconductor structure comprising a semiconductor substrate, a buried oxide layer (BOX) formed over the semiconductor substrate, and a silicon on insulator layer (SOI) formed over and in contact with the BOX layer. The SOI layer comprises shallow trench isolation (STI) structures formed between electrical devices. A first photoresist layer is formed over the STI structures and the electrical devices. Portions of said first photoresist layer, portions of the STI structures, and portions of the BOX layer are removed resulting in formed trenches. Ion implants are formed within portions of the semiconductor substrate. Remaining portions of the first photoresist layer are removed. A dielectric layer is formed over the electrical devices and within the trenches. A second photoresist layer is formed over the dielectric layer. Portions of the second photoresist layer are removed.

Abstract: An electrical structure and method of forming. The method includes providing a semiconductor structure comprising a semiconductor substrate, a buried oxide layer (BOX) formed over the semiconductor substrate, and a silicon on insulator layer (SOI) formed over and in contact with the BOX layer. The SOI layer comprises shallow trench isolation (STI) structures formed between electrical devices. A first photoresist layer is formed over the STI structures and the electrical devices. Portions of said first photoresist layer, portions of the STI structures, and portions of the BOX layer are removed resulting in formed trenches. Ion implants are formed within portions of the semiconductor substrate. Remaining portions of the first photoresist layer are removed. A dielectric layer is formed over the electrical devices and within the trenches. A second photoresist layer is formed over the dielectric layer. Portions of the second photoresist layer are removed.

Abstract: An ESD clamping circuit arranged in a darlington configuration and constructed from SiGe or similar type material. The ESD clamping circuit includes additional level shifting circuitry in series with either the trigger or clamping device or both, thus allowing non-native voltages that exceed the BVCEO of the trigger and/or clamp devices.

Abstract: An ESD clamping circuit arranged in a darlington configuration and constructed from SiGe or similar type material. The ESD clamping circuit includes additional level shifting circuitry in series with either the trigger or clamping device or both, thus allowing non-native voltages that exceed the BVCEO of the trigger and/or clamp devices.