Abstract: Methods, systems, and apparatus for processing packet fragments for reassembly into packets. Datastreams containing packet fragments are received and data corresponding to different channels are segregated. For each channel, data is then aggregated to recreate packet fragments. Once the fragments are recreated, they are, if required, resequenced using a two-tier memory mapping structure where only pointers, and not the fragments, are manipulated. After resequencing fragments to reassemble the packet, the reassembled packet is dispatched to its ultimate destination. The present invention also provides a method of load balancing between multiple links when packet fragments are transmitted from a fragmenting node through a multiple link bundle.

Abstract: Methods, systems, and apparatus for processing packet fragments for reassembly into packets. Datastreams containing packet fragments are received and data corresponding to different channels are segregated. For each channel, data is then aggregated to recreate packet fragments. Once the fragments are recreated, they are, if required, resequenced using a two-tier memory mapping structure where only pointers, and not the fragments, are manipulated. After resequencing fragments to reassemble the packet, the reassembled packet is dispatched to its ultimate destination. The present invention also provides a method of load balancing between multiple links when packet fragments are transmitted from a fragmenting node through a multiple link bundle.

Abstract: A method and apparatus for detecting framing alignment sequence within a received bit stream. A stream state memory is assigned for each possible location of the framing alignment sequence. Bits of a particular stream are loaded into the respective stream state memory. If the bits do not match an acceptable subsequence of the framing alignment sequence then the stream is eliminated from consideration by writing an exile state to the respective stream state memory. Then subsequently received bits are used to transition either to the next state if the next bit is a correct bit in the framing alignment sequence, or to the exile state if the bit is not the correct bit. After all of the streams have been exiled but one, the remaining stream may contain the framing alignment sequence. However, it may be that a certain number of correctly received bits are required to declare in-frame with sufficient certainty in which case incoming bits will continue to be processed until this is satisfied.

Abstract: The invention resides in the field of transferring data and other information from multiple asynchronous TDM channels across a synchronous interface in digital blocks of a preset length. Presently, transfer of data and timing information requires serial transmission of frame payload, qualified with clock and frame pulse indications. A separate set of these signals is required in both directions for each port or physical link. An interface of the invention permits data transfer in blocks which are uniquely identified for a specific port or links and the position of the block within the frame (if the transfer is one of framed data). The invention greatly reduces the number of required signals, thus enabling reduction of pin count requirements and an increase in the number of serviced ports.

Abstract: A technique of processing multiple digital signal streams uses one instantiation of an algorithm with memory storage of the next state, to facilitate context switching. In one embodiment, the invention is applied to framing and mapping techniques, resulting in a low circuit count for implementation with excellent performance, when measured with the commonly accepted criteria.