Abstract: A semiconductor device including a conductive substrate, an insulator layer, a silicon layer doped with impurities and forming a first transistor and a second transistor, an isolation volume between said first transistor and said second transistor, and a conductive stud extending from the doped silicon layer to the substrate.

Abstract: The present invention is a decoupling capacitor for an integrated circuit. The integrated circuit has a final metal layer which includes a power bus. The decoupling capacitor includes a dielectric film disposed over the final metal layer and a conductive film disposed over the dielectric layer, whereby capacitance may be provided in the dielectric layer.

Abstract: A method and apparatus for handling variable data word widths and array depths in an array built-in self-test system for testing a plurality of memory arrays using a single controller. Each array includes a predetermined row and column address depth and data word width. Each array further includes a scan register. A universal test data word is generated and sent to the scan register of each array. The universal length test data word has a length dependent upon the maximum row address depth, maximum column address depth and/or the maximum data word width. A portion of the test data word which exceeds the column address depth, row address depth and/or the data word width of a particular array is shifted off the end of the scan register of the particular array.

Abstract: A multi-threaded memory (and associated method) for use in a multi-threaded computer system in which plural threads are used with a single processor. The multi-threaded memory includes: multi-threaded storage cells; at least one write decoder supplying information to a selected multi-threaded storage cell; and at least one read decoder accessing information from a selected multi-threaded storage cell. Each of the multi-threaded storage cells includes: N storage elements, where N.gtoreq.2, each of the N storage elements having a thread-correspondent content; a write interface supplying information to the intra-cell storage elements; and a read interface reading information from the intra-cell storage elements. At least one of the intra-cell read and write interfaces selects one of the thread-correspondent contents based at least in part by identifying the corresponding thread to achieve intra-cell thread-correspondent content selection.