Patents by Inventor Alan Cuthbertson
Alan Cuthbertson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11952267Abstract: A modification to rough polysilicon using ion implantation and silicide is provided herein. A method can comprise depositing a hard mask on a single crystal silicon, patterning the hard mask, and depositing metal on the single crystal silicon. The method also can comprise forming silicide based on causing the metal to react with exposed silicon of the single crystal silicon. Further, the method can comprise removing unreacted metal and stripping the hard mask from the single crystal silicon. Another method can comprise forming a MEMS layer based on fusion bonding a handle MEMS with a device layer. The method also can comprise implanting rough polysilicon on the device layer. Implanting the rough polysilicon can comprise performing ion implantation of the rough polysilicon. Further, the method can comprise performing high temperature annealing. The high temperature can comprise a temperature in a range between around 700 and 1100 degrees Celsius.Type: GrantFiled: January 26, 2022Date of Patent: April 9, 2024Assignee: INVENSENSE, INC.Inventors: Alan Cuthbertson, Daesung Lee
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Patent number: 11919769Abstract: A method includes fusion bonding a handle wafer to a first side of a device wafer. The method further includes depositing a first mask on a second side of the device wafer, wherein the second side is planar. A plurality of dimple features is formed on an exposed portion on the second side of the device wafer. The first mask is removed from the second side of the device wafer. A second mask is deposited on the second side of the device wafer that corresponds to a standoff. An exposed portion on the second side of the device wafer is etched to form the standoff. The second mask is removed. A rough polysilicon layer is deposited on the second side of the device wafer. A eutectic bond layer is deposited on the standoff. In some embodiments, a micro-electro-mechanical system (MEMS) device pattern is etched into the device wafer.Type: GrantFiled: November 29, 2022Date of Patent: March 5, 2024Assignee: InvenSense, Inc.Inventors: Ashfaque Uddin, Daesung Lee, Alan Cuthbertson
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Patent number: 11905170Abstract: A method includes tab dicing a region of a tab region disposed between a first die and a second die. The tab region structurally connects the first die to the second die each including a MEMS device eutecticly bonded to a CMOS device. The tab region includes a handle wafer layer disposed over a fusion bond oxide layer that is disposed on an ACT layer. The tab region is positioned above a CMOS tab region that with the first and second die form a cavity therein. The tab dicing cuts through the handle wafer layer and leaves a portion of the fusion bond oxide layer underneath the handle wafer layer to form an oxide tether within the tab region. The oxide tether maintains the tab region in place and above the CMOS tab region. Subsequent to the tab dicing the first region, the tab region is removed.Type: GrantFiled: December 10, 2021Date of Patent: February 20, 2024Assignee: InvenSense, Inc.Inventors: Daesung Lee, Alan Cuthbertson
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Patent number: 11731871Abstract: A method includes forming an etch stop layer over a first side of a device wafer. The method also includes forming a polysilicon layer over the etch stop layer. A handle wafer is fusion bonded to the first side of the device wafer. A eutectic bond layer is formed on a second side of the device wafer. A micro-electro-mechanical system (MEMS) features are etched into the second side of the device wafer to expose the etch stop layer. The exposed etch stop layer is removed to expose the polysilicon layer. The exposed polysilicon layer is removed to expose a cavity formed between the handle wafer and the device wafer.Type: GrantFiled: May 28, 2021Date of Patent: August 22, 2023Assignee: InvenSense, Inc.Inventors: Ashfaque Uddin, Daesung Lee, Alan Cuthbertson
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Publication number: 20230202835Abstract: A method including fusion bonding a handle wafer to a first side of a device wafer. The method further includes depositing a hardmask on a second side of the device wafer, wherein the second side is planar. An etch stop layer is deposited over the hardmask and an exposed portion of the second side of the device wafer. A dielectric layer is formed over the etch stop layer. A via is formed within the dielectric layer. The via is filled with conductive material. A eutectic bond layer is formed over the conductive material. Portions of the dielectric layer uncovered by the eutectic bond layer is etched to expose the etch stop layer. The exposed portions of the etch stop layer is etched. A micro-electro-mechanical system (MEMS) device pattern is etched into the device wafer.Type: ApplicationFiled: February 28, 2023Publication date: June 29, 2023Inventors: Daesung Lee, Alan Cuthbertson
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Patent number: 11661332Abstract: Methods and systems for reducing stiction through roughening the surface and reducing the contact area in MEMS devices are disclosed. A method includes fabricating bumpstops on a surface of a MEMS device substrate to reduce stiction. Another method is directed to applying roughening etchant to a surface of a silicon substrate to enhance roughness after cavity etch and before removal of hardmask. Another embodiment described herein is directed to a method to reduce contact area between proof mass and UCAV (“upper cavity”) substrate surface with minimal impact on the cavity volume by introducing a shallow etch process step and maintaining high pressure in accelerometer cavity. Another method is described as to increasing the surface roughness of a UCAV substrate surface by depositing a rough layer (e.g. polysilicon) on the surface of the substrate and etching back the rough layer to transfer the roughness.Type: GrantFiled: February 19, 2020Date of Patent: May 30, 2023Assignee: InvenSense, Inc.Inventors: Daesung Lee, Ian Flader, Alan Cuthbertson, Emad Mehdizadeh
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Patent number: 11618674Abstract: A method including fusion bonding a handle wafer to a first side of a device wafer. The method further includes depositing a hardmask on a second side of the device wafer, wherein the second side is planar. An etch stop layer is deposited over the hardmask and an exposed portion of the second side of the device wafer. A dielectric layer is formed over the etch stop layer. A via is formed within the dielectric layer. The via is filled with conductive material. A eutectic bond layer is formed over the conductive material. Portions of the dielectric layer uncovered by the eutectic bond layer is etched to expose the etch stop layer. The exposed portions of the etch stop layer is etched. A micro-electro-mechanical system (MEMS) device pattern is etched into the device wafer.Type: GrantFiled: March 8, 2021Date of Patent: April 4, 2023Assignee: InvenSense, Inc.Inventors: Daesung Lee, Alan Cuthbertson
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Publication number: 20230100960Abstract: A method includes fusion bonding a handle wafer to a first side of a device wafer. The method further includes depositing a first mask on a second side of the device wafer, wherein the second side is planar. A plurality of dimple features is formed on an exposed portion on the second side of the device wafer. The first mask is removed from the second side of the device wafer. A second mask is deposited on the second side of the device wafer that corresponds to a standoff. An exposed portion on the second side of the device wafer is etched to form the standoff. The second mask is removed. A rough polysilicon layer is deposited on the second side of the device wafer. A eutectic bond layer is deposited on the standoff. In some embodiments, a micro-electromechanical system (MEMS) device pattern is etched into the device wafer.Type: ApplicationFiled: November 29, 2022Publication date: March 30, 2023Inventors: Ashfaque Uddin, Daesung Lee, Alan Cuthbertson
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Publication number: 20230072421Abstract: A compound of general formula (I): wherein: n is 1, 2 or 3; R1, R2, R3 and R4, independently represent OH or Q; and 20 Q represents a tissue-targeting moeity selected from the group consisting of or a stereoisomer, a hydrate, a solvate, or a salt thereof, or a mixture of same, methods of preparing said compounds, intermediate compounds useful for preparing said compounds, pharmaceutical compositions and combinations comprising said compounds and the use of said 25 compounds for manufacturing pharmaceutical compositions for the treatment or prophylaxis of diseases, in particular of soft tissue diseases, as a sole agent or in combination with other active ingredients.Type: ApplicationFiled: July 24, 2020Publication date: March 9, 2023Applicants: Bayer AS, Bayer AktiengesellschaftInventors: Niels BÖHNKE, Sabine ZITZMANN-KOLBE, Stefanie HAMMER, Sven WITTROCK, Donald BIERER, Thorsten POETHKO, Hans BRIEM, Holger Magnus STEUBER, Martina SCHÄFER, Robin Michael MEIER, Arif CELIK, Cornelia PREUSSE, Antje ROTTMANN, Nicolas WERBECK, Alexander KRISTIAN, Bård INDREVOLL, Alan CUTHBERTSON, Alex PAPPLE
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Publication number: 20230045563Abstract: A device includes a substrate comprising a first standoff, a second standoff, a third standoff, a first cavity, a second cavity, and a bonding material covering a portion of the first, the second, and the third standoff. The first cavity is positioned between the first and the second standoffs, and the second cavity is positioned between the second and the third standoffs. The first cavity comprises a first cavity region and a second cavity region separated by a portion of the substrate extruding thereto, and wherein a depth associated with the first cavity region is greater than a depth associated with the second cavity. A surface of the first cavity is covered with a getter material.Type: ApplicationFiled: July 29, 2022Publication date: February 9, 2023Inventors: Daesung Lee, Alan Cuthbertson
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Publication number: 20230037849Abstract: A method includes forming a bumpstop from a first intermetal dielectric (IMD) layer and forming a via within the first IMD, wherein the first IMD is disposed over a first polysilicon layer, and wherein the first polysilicon layer is disposed over another IMD layer that is disposed over a substrate. The method further includes depositing a second polysilicon layer over the bumpstop and further over the via to connect to the first polysilicon layer. A standoff is formed over a first portion of the second polysilicon layer, and wherein a second portion of the second polysilicon layer is exposed. The method includes depositing a bond layer over the standoff.Type: ApplicationFiled: July 29, 2022Publication date: February 9, 2023Inventors: Daesung Lee, Alan Cuthbertson
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Publication number: 20230045257Abstract: A device includes a substrate and an intermetal dielectric (IMD) layer disposed over the substrate. The device also includes a first plurality of polysilicon layers disposed over the IMD layer and over a bumpstop. The device also includes a second plurality of polysilicon layers disposed within the IMD layer. The device includes a patterned actuator layer with a first side and a second side, wherein the first side of the patterned actuator layer is lined with a polysilicon layer, and wherein the first side of the patterned actuator layer faces the bumpstop. The device further includes a standoff formed over the IMD layer, a via through the standoff making electrical contact with the polysilicon layer of the actuator and a portion of the second plurality of polysilicon layers and a bond material disposed on the second side of the patterned actuator layer.Type: ApplicationFiled: July 29, 2022Publication date: February 9, 2023Inventors: Daesung Lee, Alan Cuthbertson
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Patent number: 11542154Abstract: A method includes fusion bonding a handle wafer to a first side of a device wafer. The method further includes depositing a first mask on a second side of the device wafer, wherein the second side is planar. A plurality of dimple features is formed on an exposed portion on the second side of the device wafer. The first mask is removed from the second side of the device wafer. A second mask is deposited on the second side of the device wafer that corresponds to a standoff. An exposed portion on the second side of the device wafer is etched to form the standoff. The second mask is removed. A rough polysilicon layer is deposited on the second side of the device wafer. A eutectic bond layer is deposited on the standoff. In some embodiments, a micro-electro-mechanical system (MEMS) device pattern is etched into the device wafer.Type: GrantFiled: March 18, 2021Date of Patent: January 3, 2023Assignee: InvenSense, Inc.Inventors: Ashfaque Uddin, Daesung Lee, Alan Cuthbertson
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Publication number: 20220380209Abstract: A method includes forming an etch stop layer over a first side of a device wafer. The method also includes forming a polysilicon layer over the etch stop layer. A handle wafer is fusion bonded to the first side of the device wafer. A eutectic bond layer is formed on a second side of the device wafer. A micro-electro-mechanical system (MEMS) features are etched into the second side of the device wafer to expose the etch stop layer. The exposed etch stop layer is removed to expose the polysilicon layer. The exposed polysilicon layer is removed to expose a cavity formed between the handle wafer and the device wafer.Type: ApplicationFiled: May 28, 2021Publication date: December 1, 2022Inventors: Ashfaque Uddin, Daesung Lee, Alan Cuthbertson
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Publication number: 20220298009Abstract: A method includes fusion bonding a handle wafer to a first side of a device wafer. The method further includes depositing a first mask on a second side of the device wafer, wherein the second side is planar. A plurality of dimple features is formed on an exposed portion on the second side of the device wafer. The first mask is removed from the second side of the device wafer. A second mask is deposited on the second side of the device wafer that corresponds to a standoff. An exposed portion on the second side of the device wafer is etched to form the standoff. The second mask is removed. A rough polysilicon layer is deposited on the second side of the device wafer. A eutectic bond layer is deposited on the standoff. In some embodiments, a micro-electro-mechanical system (MEMS) device pattern is etched into the device wafer.Type: ApplicationFiled: March 18, 2021Publication date: September 22, 2022Inventors: Ashfaque Uddin, Daesung Lee, Alan Cuthbertson
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Publication number: 20220185662Abstract: A method includes tab dicing a region of a tab region disposed between a first die and a second die. The tab region structurally connects the first die to the second die each including a MEMS device eutecticly bonded to a CMOS device. The tab region includes a handle wafer layer disposed over a fusion bond oxide layer that is disposed on an ACT layer. The tab region is positioned above a CMOS tab region that with the first and second die form a cavity therein. The tab dicing cuts through the handle wafer layer and leaves a portion of the fusion bond oxide layer underneath the handle wafer layer to form an oxide tether within the tab region. The oxide tether maintains the tab region in place and above the CMOS tab region. Subsequent to the tab dicing the first region, the tab region is removed.Type: ApplicationFiled: December 10, 2021Publication date: June 16, 2022Inventors: Daesung Lee, Alan Cuthbertson
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Publication number: 20220144628Abstract: A modification to rough polysilicon using ion implantation and silicide is provided herein. A method can comprise depositing a hard mask on a single crystal silicon, patterning the hard mask, and depositing metal on the single crystal silicon. The method also can comprise forming silicide based on causing the metal to react with exposed silicon of the single crystal silicon. Further, the method can comprise removing unreacted metal and stripping the hard mask from the single crystal silicon. Another method can comprise forming a MEMS layer based on fusion bonding a handle MEMS with a device layer. The method also can comprise implanting rough polysilicon on the device layer. Implanting the rough polysilicon can comprise performing ion implantation of the rough polysilicon. Further, the method can comprise performing high temperature annealing. The high temperature can comprise a temperature in a range between around 700 and 1100 degrees Celsius.Type: ApplicationFiled: January 26, 2022Publication date: May 12, 2022Inventors: Alan Cuthbertson, Daesung Lee
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Publication number: 20220143229Abstract: The invention provides a method for the formation of a tissue-targeting thorium complex, said method comprising; a) forming an octadentate chelator comprising four hydroxypyridinone (HOPO) moieties, substituted in the N-position with a methyl group, and a coupling moiety terminating in a carboxylic acid group; b) coupling said octadentate chelator to at least one tissue-targeting moiety targeting HER2; and c) contacting said tissue-targeting chelator with an aqueous solution comprising an ion of at least one alpha-emitting thorium isotope.Type: ApplicationFiled: January 21, 2022Publication date: May 12, 2022Applicants: Bayer Pharma Aktiengesellschaft, Bayer ASInventors: Lars LINDEN, Alan CUTHBERTSON
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Publication number: 20220125960Abstract: The present invention relates to combinations of at least two components, component A and component B, component A being a PD-1/PD-L1 inhibitor, and component B being a targeted thorium conjugate. Another aspect of the present invention relates to the use of such combinations as described herein for the preparation of a medicament for the treatment or prophylaxis of a disease, particularly for the treatment of breast and prostate cancer.Type: ApplicationFiled: February 17, 2020Publication date: April 28, 2022Applicants: Bayer Aktiengesellschaft, Bayer ASInventors: Urs Beat HAGEMANN, Pascale LEJEUNE, Jenny KARLSSON, Alan CUTHBERTSON, Stefanie HAMMER
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Publication number: 20220106188Abstract: A method including fusion bonding a handle wafer to a first side of a device wafer. The method further includes depositing a hardmask on a second side of the device wafer, wherein the second side is planar. An etch stop layer is deposited over the hardmask and an exposed portion of the second side of the device wafer. A dielectric layer is formed over the etch stop layer. A via is formed within the dielectric layer. The via is filled with conductive material. A eutectic bond layer is formed over the conductive material. Portions of the dielectric layer uncovered by the eutectic bond layer is etched to expose the etch stop layer. The exposed portions of the etch stop layer is etched. A micro-electro-mechanical system (MEMS) device pattern is etched into the device wafer.Type: ApplicationFiled: March 8, 2021Publication date: April 7, 2022Inventors: Daesung Lee, Alan Cuthbertson