Patents by Inventor Alan D. Bennett

Alan D. Bennett has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11226761
    Abstract: The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller and a storage unit divided into a plurality of zones. Each zone comprises a plurality of dies, where each die comprises a plurality of erase blocks. Each erase block comprises a plurality of wordlines. One or more wordlines are grouped together in bins. Each bin is associated with a susceptibility weight, a read count weight, a timer count weight, and a running total weight. A weight counter table is stored in the controller, and tracks the various weights associated with each bin. When a sum of the weights of each bin reaches or exceeds a predetermined value, the controller closes the erase block to avoid an unacceptable quantity of bit error accumulation. The bit error susceptibility of an erase block decreases after the erase block is at capacity or is closed.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: January 18, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Liam Parker, Daniel L. Helmick, Alan D. Bennett, Sergey Anatolievich Gorobets
  • Patent number: 11209989
    Abstract: The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller and a media unit. The capacity of the media unit is divided into a plurality of zones. The controller is configured to make informed use of errors by update zone metadata to indicate one or more first logical block addresses were skipped and to indicate the next valid logical block address is available to store data. The controller is further configured to update zone metadata to recommend to the host device to reset one or more full zones, to recommend to the host device to transition one or more open zones to a full state, to alert the host device that one or more open zones have been transitioned to the full state, and to notify the host device of the writeable zone capacity of each of the plurality of zones.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: December 28, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Matias Bjørling, Horst-Christoph Georg Hellwig, David Landsman, Daniel L. Helmick, Liam Parker, Alan D. Bennett, Peter Grayson, Judah Gamliel Hahn
  • Patent number: 11211119
    Abstract: Data can be written to SLC memory. Then, the data can be decoded and then both foggy and finely written to MLC. After the decoding, the data can be stored in DRAM located in a front end or in a SRAM located in a flash manager prior to being written to MLC. After storing in either the DRAM or SRAM, the data is then decoded and written to MLC.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: December 28, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Sergey Anatolievich Gorobets, Alan D. Bennett, Thomas Hugh Shippey, Ryan R. Jones
  • Publication number: 20210391002
    Abstract: Data can be written to SLC memory. Then, the data can be decoded and then both foggy and finely written to MLC. After the decoding, the data can be stored in DRAM located in a front end or in a SRAM located in a flash manager prior to being written to MLC. After storing in either the DRAM or SRAM, the data is then decoded and written to MLC.
    Type: Application
    Filed: June 11, 2020
    Publication date: December 16, 2021
    Inventors: Sergey Anatolievich GOROBETS, Alan D. BENNETT, Thomas Hugh SHIPPEY, Ryan R. JONES
  • Patent number: 11200162
    Abstract: The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller, random-access memory (RAM), and a NVM unit, where in the NVM unit comprises a plurality of zones. The RAM unit comprises a logical to physical address (L2P) table for the plurality of zones. The L2P table comprises pointers that are associated with a logical block address (LBA) and the physical location of the data stored in the NVM. The L2P table comprises one pointer per erase block or zone. When a command is received to read data within the NVM, the controller reads the L2P table to determine the LBA and associated pointer of the data. The controller can then determine which zone or erase block the data is stored in, and calculates various offsets of wordlines, pages, and page addresses to find the exact location of the data in the NVM.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: December 14, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Daniel L. Helmick, Liam Parker, Alan D. Bennett, Horst-Christoph Georg Hellwig
  • Patent number: 11200161
    Abstract: The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller and a media unit divided into a plurality of zones. Data associated with one or more first commands is written to a first portion of a first zone. Upon a predetermined amount of time passing, dummy data is written to a second portion of the first zone to fill the first zone to a zone capacity. Upon receiving one or more second commands to write data, a second zone is allocated and opened, and the data associated with the one or more second commands is written to a first portion of the second zone. The data associated with the one or more first commands is then optionally re-written to a second portion of the second zone to fill the second zone to a zone capacity, and the first zone is erased.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: December 14, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Alan D. Bennett, Liam Parker, Daniel L. Helmick
  • Publication number: 20210374003
    Abstract: The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller comprising first random access memory (RAM1), second random access memory (RAM2), and a storage unit divided into a plurality of zones. A first command to write data to a first zone is received, first XOR data is generated in the RAM1, and the data of the first command is written to the first zone. When a second command to write data to a second zone is received, the generated first XOR data is copied from the RAM1 to the RAM2, and second XOR data for the second zone is copied from the RAM2 to the RAM1. The second XOR data is updated with the second command, and the data of the second command is written to the second zone. The updated second XOR data is copied from the RAM1 to the RAM2.
    Type: Application
    Filed: May 27, 2020
    Publication date: December 2, 2021
    Applicant: Western Digital Technologies, Inc.
    Inventors: Daniel L. HELMICK, Liam PARKER, Alan D. BENNETT, Peter GRAYSON, Sergey Anatolievich GOROBETS
  • Publication number: 20210334041
    Abstract: The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller and a storage unit divided into a plurality of zones. The storage unit comprises a plurality of dies, where each die comprises two planes. One erase block from each plane of a die is selected for zone formation. Each erase block comprises a plurality of wordlines. A zone comprises one or two dies dedicated to storing parity data and a plurality of dies dedicated to storing user data. The zone further comprises space devoted for controller metadata. The storage device restricts a host device to send write commands in a minimum write size to increase programming efficiency. The minimum write size equals one wordline from one erase block from each plane of each die in the zone dedicated to storing user data minus the space dedicated to metadata.
    Type: Application
    Filed: April 24, 2020
    Publication date: October 28, 2021
    Applicant: Western Digital Technologies, Inc.
    Inventors: Alan D. BENNETT, Daniel L. HELMICK, Liam PARKER, Sergey Anatolievich GOROBETS, Peter GRAYSON
  • Publication number: 20210334203
    Abstract: The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller, random-access memory (RAM), and a NVM unit, where in the NVM unit comprises a plurality of zones. The RAM unit comprises a logical to physical address (L2P) table for the plurality of zones. The L2P table comprises pointers that are associated with a logical block address (LBA) and the physical location of the data stored in the NVM. The L2P table comprises one pointer per erase block or zone. When a command is received to read data within the NVM, the controller reads the L2P table to determine the LBA and associated pointer of the data. The controller can then determine which zone or erase block the data is stored in, and calculates various offsets of wordlines, pages, and page addresses to find the exact location of the data in the NVM.
    Type: Application
    Filed: April 28, 2020
    Publication date: October 28, 2021
    Applicant: Western Digital Technologies, Inc.
    Inventors: Daniel L. HELMICK, Liam PARKER, Alan D. BENNETT, Horst-Christoph Georg HELLWIG
  • Publication number: 20210334032
    Abstract: The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller and a storage unit divided into a plurality of zones. Each zone comprises a plurality of dies, where each die comprises a plurality of erase blocks. Each erase block comprises a plurality of wordlines. One or more wordlines are grouped together in bins. Each bin is associated with a susceptibility weight, a read count weight, a timer count weight, and a running total weight. A weight counter table is stored in the controller, and tracks the various weights associated with each bin. When a sum of the weights of each bin reaches or exceeds a predetermined value, the controller closes the erase block to avoid an unacceptable quantity of bit error accumulation. The bit error susceptibility of an erase block decreases after the erase block is at capacity or is closed.
    Type: Application
    Filed: April 24, 2020
    Publication date: October 28, 2021
    Applicant: Western Digital Technologies, Inc.
    Inventors: Liam PARKER, Daniel L. HELMICK, Alan D. BENNETT, Sergey Anatolievich GOROBETS
  • Publication number: 20210334201
    Abstract: The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller and a storage unit divided into a plurality of streams. The storage unit comprises a plurality of dies, where each die comprises two planes. One erase block from each plane of a die is selected for stream formation. Each erase block comprises a plurality of wordlines. A stream comprises one or two dies dedicated to storing parity data and a plurality of dies dedicated to storing user data. The stream further comprises space devoted for controller metadata. The storage device restricts a host device to send write commands in a minimum write size to increase programming efficiency. The minimum write size equals one wordline from one erase block from each plane of each die in the stream dedicated to storing user data minus the space dedicated to metadata.
    Type: Application
    Filed: April 24, 2020
    Publication date: October 28, 2021
    Applicant: Western Digital Technologies, Inc.
    Inventors: Alan D. BENNETT, Daniel L. HELMICK, Liam PARKER, Sergey Anatolievich GOROBETS, Peter GRAYSON
  • Publication number: 20210326250
    Abstract: The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller and a media unit divided into a plurality of zones. Data associated with one or more first commands is written to a first portion of a first zone. Upon a predetermined amount of time passing, dummy data is written to a second portion of the first zone to fill the first zone to a zone capacity. Upon receiving one or more second commands to write data, a second zone is allocated and opened, and the data associated with the one or more second commands is written to a first portion of the second zone. The data associated with the one or more first commands is then optionally re-written to a second portion of the second zone to fill the second zone to a zone capacity, and the first zone is erased.
    Type: Application
    Filed: April 20, 2020
    Publication date: October 21, 2021
    Applicant: Western Digital Technologies, Inc.
    Inventors: Alan D. BENNETT, Liam PARKER, Daniel L. HELMICK
  • Patent number: 11137944
    Abstract: The present disclosure generally relates to improved foggy-fine programming. The data to be written initially passes through an encoder before being written to SLC. While the data is being written to SLC, the data also passes through DRAM before going through the encoder to prepare for fine writing. The data that is to be stored in SLC is in latches in the memory device and is then written to MLC as a foggy write. Thereafter, the data that has passed through the encoder is fine written to MLC. The programming occurs in a staggered fashion where the ratio of SLC:foggy:fine writing is 4:1:1. To ensure sufficient XOR context management, programming across multiple dies, as well as across multiple super-devices, is staggered so that only four XOR parity context are necessary across 64 dies.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: October 5, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Sergey Anatolievich Gorobets, Alan D. Bennett, Ryan R. Jones
  • Patent number: 11138066
    Abstract: The A storage device comprises a controller comprising first random access memory (RAM1), second random access memory (RAM2), and a storage unit divided into a plurality of streams. A first command to write data to a first stream is received, first XOR data is generated in the RAM1, and the data of the first command is written to the first stream. When a second command to write data to a second stream is received, the generated first XOR data is copied from the RAM1 to the RAM2, and second XOR data for the second stream is copied from the RAM2 to the RAM1. The second XOR data is updated with the second command, and the data of the second command is written to the second stream. The updated second XOR data is copied from the RAM1 to the RAM2.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: October 5, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Sergey Anatolievich Gorobets, Daniel L. Helmick, Liam Parker, Alan D. Bennett, Peter Grayson
  • Publication number: 20210286554
    Abstract: The present disclosure generally relates to improved foggy-fine programming. The data to be written initially passes through an encoder before being written to SLC. While the data is being written to SLC, the data also passes through DRAM before going through the encoder to prepare for fine writing. The data that is to be stored in SLC is in latches in the memory device and is then written to MLC as a foggy write. Thereafter, the data that has passed through the encoder is fine written to MLC. The programming occurs in a staggered fashion where the ratio of SLC:foggy:fine writing is 4:1:1. To ensure sufficient XOR context management, programming across multiple dies, as well as across multiple super-devices, is staggered so that only four XOR parity context are necessary across 64 dies.
    Type: Application
    Filed: March 13, 2020
    Publication date: September 16, 2021
    Inventors: Sergey Anatolievich GOROBETS, Alan D. BENNETT, Ryan R. JONES
  • Publication number: 20210089217
    Abstract: The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller and a media unit. The capacity of the media unit is divided into a plurality of zones. The controller is configured to make informed use of errors by update zone metadata to indicate one or more first logical block addresses were skipped and to indicate the next valid logical block address is available to store data. The controller is further configured to update zone metadata to recommend to the host device to reset one or more full zones, to recommend to the host device to transition one or more open zones to a full state, to alert the host device that one or more open zones have been transitioned to the full state, and to notify the host device of the writeable zone capacity of each of the plurality of zones.
    Type: Application
    Filed: December 27, 2019
    Publication date: March 25, 2021
    Inventors: Matias BJØRLING, Horst-Christoph Georg HELLWIG, David LANDSMAN, Daniel L. HELMICK, Liam PARKER, Alan D. BENNETT, Peter GRAYSON, Judah Gamliel HAHN
  • Publication number: 20210081330
    Abstract: The present disclosure generally relates to methods of operating storage devices. A controller of the storage device is configured to retrieve a first command to write data to one or more first logical blocks of a first zone, and direct memory access (DMA) read and write the data associated with the first command to the first logical blocks. The first logical blocks are between a zone starting point of the first zone and a zone capacity of the first zone. The controller is configured to retrieve a second command to write data to one or more second logical blocks of the first zone, and DMA read and write the data associated with the second command to the second logical blocks. The second logical blocks are between the zone starting and the zone capacity of the first zone, and the first logical blocks are non-sequential to the second logical blocks.
    Type: Application
    Filed: December 4, 2019
    Publication date: March 18, 2021
    Inventors: Alan D. BENNETT, Matias BJORLING, Daniel L. HELMICK
  • Publication number: 20200409589
    Abstract: The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller and a media unit. The capacity of the media unit is divided into a plurality of zones. The media unit comprises a plurality of dies, and each of the plurality of dies comprising a plurality of erase blocks. The controller is configured to compare an estimated age of a first available erase block in each of the plurality of dies to one another and select one or more of the first available erase blocks from one or more dies of the plurality of dies based on the estimated ages to form a first zone. At least one first available erase block from at least one die of the plurality of die is excluded from the first zone.
    Type: Application
    Filed: December 4, 2019
    Publication date: December 31, 2020
    Inventors: Alan D. BENNETT, Liam PARKER, Daniel L. HELMICK, Sergey Anatolievich GOROBETS, Peter GRAYSON
  • Patent number: 8533562
    Abstract: A portion of a nonvolatile memory array that is likely to contain, partially programmed data may be identified from a high sensitivity read, by applying stricter than usual ECC requirements, or using pointers to programmed sectors. The last programmed data may be treated as likely to be partially programmed data. Data in the identified portion may be copied to another location, or left where it is with an indicator to prohibit further programming to the same cells. To avoid compromising previously stored data during subsequent programming, previously stored data may be backed up. Backing up may be done selectively, for example, only for nonsequential data, or only when the previously stored data contains an earlier version of data being programmed. If a backup copy already exists, another backup copy is not created. Sequential commands are treated as a single command if received within a predetermined time period.
    Type: Grant
    Filed: February 5, 2008
    Date of Patent: September 10, 2013
    Assignee: SanDisk Technologies Inc.
    Inventors: Bryan J. Mee, Yosief Ataklti, Alan D. Bennett
  • Patent number: 8266391
    Abstract: A method for writing data to a memory device is disclosed. In one embodiment, data of an atomic transaction is written to a first memory in a memory device. A determination is made regarding whether all of the data of the atomic transaction was written to the first memory. The data of the atomic transaction is read from the first memory and written to a second memory in the memory device only if it is determined that all of the data of the atomic transaction was written to the first memory.
    Type: Grant
    Filed: June 19, 2007
    Date of Patent: September 11, 2012
    Assignee: SanDisk Technologies, Inc.
    Inventors: Andrew Tomlin, Sergey A. Gorobets, Reuven Elhamias, Shai Traister, Alan D. Bennett