Patents by Inventor Alan D. Bennett
Alan D. Bennett has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240086097Abstract: The present disclosure generally relates to improving programming to data storage devices, such as solid state drives (SSDs). A first memory device has a first XOR element and a second memory device has a second XOR element. The ratio of the first XOR element to the capacity of the first memory device is substantially smaller than the ratio of the second XOR element to the capacity of the second memory device. A read verify operation to find program failures is executed on either a wordline to wordline basis, an erase block to erase block basis, or both a wordline to wordline basis and an erase block to erase block basis. Because the program failures are found and fixed prior to programming to the second memory device, the second XOR element may be decreased substantially.Type: ApplicationFiled: November 21, 2023Publication date: March 14, 2024Applicant: Western Digital Technologies, Inc.Inventors: Sergey Anatolievich GOROBETS, Alan D. BENNETT, Liam PARKER, Yuval SHOHET, Michelle MARTIN
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Patent number: 11861195Abstract: The present disclosure generally relates to improving programming to data storage devices, such as solid state drives (SSDs). A first memory device has a first XOR element and a second memory device has a second XOR element. The ratio of the first XOR element to the capacity of the first memory device is substantially smaller than the ratio of the second XOR element to the capacity of the second memory device. A read verify operation to find program failures is executed on either a wordline to wordline basis, an erase block to erase block basis, or both a wordline to wordline basis and an erase block to erase block basis. Because the program failures are found and fixed prior to programming to the second memory device, the second XOR element may be decreased substantially.Type: GrantFiled: March 15, 2021Date of Patent: January 2, 2024Assignee: Western Digital Technologies, Inc.Inventors: Sergey Anatolievich Gorobets, Alan D. Bennett, Liam Parker, Yuval Shohet, Michelle Martin
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Patent number: 11656984Abstract: The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller and a media unit divided into a plurality of zones. Data associated with one or more first commands is written to a first portion of a first zone. Upon a predetermined amount of time passing, dummy data is written to a second portion of the first zone to fill the first zone to a zone capacity. Upon receiving one or more second commands to write data, a second zone is allocated and opened, and the data associated with the one or more second commands is written to a first portion of the second zone. The data associated with the one or more first commands is then optionally re-written to a second portion of the second zone to fill the second zone to a zone capacity, and the first zone is erased.Type: GrantFiled: November 19, 2021Date of Patent: May 23, 2023Assignee: Western Digital Technologies, Inc.Inventors: Alan D. Bennett, Liam Parker, Daniel L. Helmick
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Patent number: 11631457Abstract: A method and system for improved foggy-fine programming includes data that can be written to SLC memory. Then, the data can be decoded and then both foggy and finely written to MLC. After the decoding, the data can be stored in DRAM located in a front end or in a SRAM located in a flash manager prior to being written to MLC. After storing in either the DRAM or SRAM, the data is then decoded and written to MLC.Type: GrantFiled: December 14, 2021Date of Patent: April 18, 2023Assignee: Western Digital Technologies, Inc.Inventors: Sergey Anatolievich Gorobets, Alan D. Bennett, Thomas Hugh Shippey, Ryan R. Jones
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Patent number: 11568938Abstract: A data storage device includes one or more memory devices that each includes one or more superblocks and a controller coupled to the one or more memory devices. Each superblock includes a plurality of wordlines. The controller is configured to write data to a first wordline of the plurality of wordlines, write data to a second wordline of the plurality of wordlines, perform a read verify operation on the first wordline, and perform a read verify operation on the second wordline. At least one of the first wordline and the second wordline does not include an XOR parity element and one or more wordlines of the plurality of wordlines includes the XOR parity element.Type: GrantFiled: February 22, 2021Date of Patent: January 31, 2023Assignee: Western Digital Technologies, Inc.Inventors: Sergey Anatolievich Gorobets, Alan D. Bennett, Liam Parker, Yuval Shohet, Michelle Martin
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Patent number: 11537510Abstract: The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller and a storage unit divided into a plurality of streams. The storage unit comprises a plurality of dies, where each die comprises two planes. One erase block from each plane of a die is selected for stream formation. Each erase block comprises a plurality of wordlines. A stream comprises one or two dies dedicated to storing parity data and a plurality of dies dedicated to storing user data. The stream further comprises space devoted for controller metadata. The storage device restricts a host device to send write commands in a minimum write size to increase programming efficiency. The minimum write size equals one wordline from one erase block from each plane of each die in the stream dedicated to storing user data minus the space dedicated to metadata.Type: GrantFiled: April 24, 2020Date of Patent: December 27, 2022Assignee: Western Digital Technologies, Inc.Inventors: Alan D. Bennett, Daniel L. Helmick, Liam Parker, Sergey Anatolievich Gorobets, Peter Grayson
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Patent number: 11500727Abstract: The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller comprising first random access memory (RAM1), second random access memory (RAM2), and a storage unit divided into a plurality of zones. A first command to write data to a first zone is received, first XOR data is generated in the RAM1, and the data of the first command is written to the first zone. When a second command to write data to a second zone is received, the generated first XOR data is copied from the RAM1 to the RAM2, and second XOR data for the second zone is copied from the RAM2 to the RAM1. The second XOR data is updated with the second command, and the data of the second command is written to the second zone. The updated second XOR data is copied from the RAM1 to the RAM2.Type: GrantFiled: May 27, 2020Date of Patent: November 15, 2022Assignee: Western Digital Technologies, Inc.Inventors: Daniel L. Helmick, Liam Parker, Alan D. Bennett, Peter Grayson, Sergey Anatolievich Gorobets
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Publication number: 20220291838Abstract: The present disclosure generally relates to improving programming to data storage devices, such as solid state drives (SSDs). A first memory device has a first XOR element and a second memory device has a second XOR element. The ratio of the first XOR element to the capacity of the first memory device is substantially smaller than the ratio of the second XOR element to the capacity of the second memory device. A read verify operation to find program failures is executed on either a wordline to wordline basis, an erase block to erase block basis, or both a wordline to wordline basis and an erase block to erase block basis. Because the program failures are found and fixed prior to programming to the second memory device, the second XOR element may be decreased substantially.Type: ApplicationFiled: March 15, 2021Publication date: September 15, 2022Inventors: Sergey Anatolievich GOROBETS, Alan D. BENNETT, Liam PARKER, Yuval SHOHET, Michelle MARTIN
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Patent number: 11416161Abstract: The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller and a media unit. The capacity of the media unit is divided into a plurality of zones. The media unit comprises a plurality of dies, and each of the plurality of dies comprising a plurality of erase blocks. The controller is configured to compare an estimated age of a first available erase block in each of the plurality of dies to one another and select one or more of the first available erase blocks from one or more dies of the plurality of dies based on the estimated ages to form a first zone. At least one first available erase block from at least one die of the plurality of die is excluded from the first zone.Type: GrantFiled: December 4, 2019Date of Patent: August 16, 2022Assignee: Western Digital Technologies, Inc.Inventors: Alan D. Bennett, Liam Parker, Daniel L. Helmick, Sergey Anatolievich Gorobets, Peter Grayson
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Publication number: 20220139466Abstract: The present disclosure generally relates to improving programming to data storage devices, such as solid state drives (SSDs). A first memory device has a first XOR element and a second memory device has a second XOR element. The ratio of the first XOR element to the capacity of the first memory device is substantially smaller than the ratio of the second XOR element to the capacity of the second memory device. A read verify operation to find program failures is executed on either a wordline to wordline basis, an erase block to erase block basis, or both a wordline to wordline basis and an erase block to erase block basis. Because the program failures are found and fixed prior to programming to the second memory device, the second XOR element may be decreased substantially.Type: ApplicationFiled: February 22, 2021Publication date: May 5, 2022Inventors: Sergey Anatolievich GOROBETS, Alan D. BENNETT, Liam PARKER, Yuval SHOHET, Michelle MARTIN
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Publication number: 20220108745Abstract: The present disclosure generally relates to improved foggy-fine programming. The data can be written to SLC memory. Then, the data can be decoded and then both foggy and finely written to MLC. After the decoding, the data can be stored in DRAM located in a front end or in a SRAM located in a flash manager prior to being written to MLC. After storing in either the DRAM or SRAM, the data is then decoded and written to MLC.Type: ApplicationFiled: December 14, 2021Publication date: April 7, 2022Applicant: Western Digital Technologies, Inc.Inventors: Sergey Anatolievich Gorobets, Alan D. Bennett, Thomas Hugh Shippey, Ryan R. Jones
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Patent number: 11294598Abstract: The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller and a storage unit divided into a plurality of zones. The storage unit comprises a plurality of dies, where each die comprises two planes. One erase block from each plane of a die is selected for zone formation. Each erase block comprises a plurality of wordlines. A zone comprises one or two dies dedicated to storing parity data and a plurality of dies dedicated to storing user data. The zone further comprises space devoted for controller metadata. The storage device restricts a host device to send write commands in a minimum write size to increase programming efficiency. The minimum write size equals one wordline from one erase block from each plane of each die in the zone dedicated to storing user data minus the space dedicated to metadata.Type: GrantFiled: April 24, 2020Date of Patent: April 5, 2022Assignee: Western Digital Technologies, Inc.Inventors: Alan D. Bennett, Daniel L. Helmick, Liam Parker, Sergey Anatolievich Gorobets, Peter Grayson
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Patent number: 11294827Abstract: The present disclosure generally relates to methods of operating storage devices. A controller of the storage device is configured to retrieve a first command to write data to one or more first logical blocks of a first zone, and direct memory access (DMA) read and write the data associated with the first command to the first logical blocks. The first logical blocks are between a zone starting point of the first zone and a zone capacity of the first zone. The controller is configured to retrieve a second command to write data to one or more second logical blocks of the first zone, and DMA read and write the data associated with the second command to the second logical blocks. The second logical blocks are between the zone starting and the zone capacity of the first zone, and the first logical blocks are non-sequential to the second logical blocks.Type: GrantFiled: December 4, 2019Date of Patent: April 5, 2022Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Alan D. Bennett, Matias Bjorling, Daniel L. Helmick
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Publication number: 20220100390Abstract: The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller and a media unit. The capacity of the media unit is divided into a plurality of zones. The controller is configured to make informed use of errors by update zone metadata to indicate one or more first logical block addresses were skipped and to indicate the next valid logical block address is available to store data. The controller is further configured to update zone metadata to recommend to the host device to reset one or more full zones, to recommend to the host device to transition one or more open zones to a full state, to alert the host device that one or more open zones have been transitioned to the full state, and to notify the host device of the writeable zone capacity of each of the plurality of zones.Type: ApplicationFiled: December 10, 2021Publication date: March 31, 2022Applicant: Western Digital Technologies, Inc.Inventors: Matias BJORLING, Horst-Christoph Georg HELLWIG, David LANDSMAN, Daniel L. HELMICK, Liam PARKER, Alan D. BENNETT, Peter GRAYSON, Judah Gamliel HAHN
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Publication number: 20220075718Abstract: The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller and a media unit divided into a plurality of zones. Data associated with one or more first commands is written to a first portion of a first zone. Upon a predetermined amount of time passing, dummy data is written to a second portion of the first zone to fill the first zone to a zone capacity. Upon receiving one or more second commands to write data, a second zone is allocated and opened, and the data associated with the one or more second commands is written to a first portion of the second zone. The data associated with the one or more first commands is then optionally re-written to a second portion of the second zone to fill the second zone to a zone capacity, and the first zone is erased.Type: ApplicationFiled: November 19, 2021Publication date: March 10, 2022Applicant: Western Digital Technologies, Inc.Inventors: Alan D. BENNETT, Liam PARKER, Daniel L. HELMICK
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Patent number: 11226761Abstract: The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller and a storage unit divided into a plurality of zones. Each zone comprises a plurality of dies, where each die comprises a plurality of erase blocks. Each erase block comprises a plurality of wordlines. One or more wordlines are grouped together in bins. Each bin is associated with a susceptibility weight, a read count weight, a timer count weight, and a running total weight. A weight counter table is stored in the controller, and tracks the various weights associated with each bin. When a sum of the weights of each bin reaches or exceeds a predetermined value, the controller closes the erase block to avoid an unacceptable quantity of bit error accumulation. The bit error susceptibility of an erase block decreases after the erase block is at capacity or is closed.Type: GrantFiled: April 24, 2020Date of Patent: January 18, 2022Assignee: Western Digital Technologies, Inc.Inventors: Liam Parker, Daniel L. Helmick, Alan D. Bennett, Sergey Anatolievich Gorobets
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Patent number: 11211119Abstract: Data can be written to SLC memory. Then, the data can be decoded and then both foggy and finely written to MLC. After the decoding, the data can be stored in DRAM located in a front end or in a SRAM located in a flash manager prior to being written to MLC. After storing in either the DRAM or SRAM, the data is then decoded and written to MLC.Type: GrantFiled: June 11, 2020Date of Patent: December 28, 2021Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Sergey Anatolievich Gorobets, Alan D. Bennett, Thomas Hugh Shippey, Ryan R. Jones
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Patent number: 11209989Abstract: The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller and a media unit. The capacity of the media unit is divided into a plurality of zones. The controller is configured to make informed use of errors by update zone metadata to indicate one or more first logical block addresses were skipped and to indicate the next valid logical block address is available to store data. The controller is further configured to update zone metadata to recommend to the host device to reset one or more full zones, to recommend to the host device to transition one or more open zones to a full state, to alert the host device that one or more open zones have been transitioned to the full state, and to notify the host device of the writeable zone capacity of each of the plurality of zones.Type: GrantFiled: December 27, 2019Date of Patent: December 28, 2021Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Matias Bjørling, Horst-Christoph Georg Hellwig, David Landsman, Daniel L. Helmick, Liam Parker, Alan D. Bennett, Peter Grayson, Judah Gamliel Hahn
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Publication number: 20210391002Abstract: Data can be written to SLC memory. Then, the data can be decoded and then both foggy and finely written to MLC. After the decoding, the data can be stored in DRAM located in a front end or in a SRAM located in a flash manager prior to being written to MLC. After storing in either the DRAM or SRAM, the data is then decoded and written to MLC.Type: ApplicationFiled: June 11, 2020Publication date: December 16, 2021Inventors: Sergey Anatolievich GOROBETS, Alan D. BENNETT, Thomas Hugh SHIPPEY, Ryan R. JONES
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Patent number: 11200161Abstract: The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller and a media unit divided into a plurality of zones. Data associated with one or more first commands is written to a first portion of a first zone. Upon a predetermined amount of time passing, dummy data is written to a second portion of the first zone to fill the first zone to a zone capacity. Upon receiving one or more second commands to write data, a second zone is allocated and opened, and the data associated with the one or more second commands is written to a first portion of the second zone. The data associated with the one or more first commands is then optionally re-written to a second portion of the second zone to fill the second zone to a zone capacity, and the first zone is erased.Type: GrantFiled: April 20, 2020Date of Patent: December 14, 2021Assignee: Western Digital Technologies, Inc.Inventors: Alan D. Bennett, Liam Parker, Daniel L. Helmick