Abstract: A single layer ceramic capacitor for wire bonding or solder or epoxy attachment wherein a bottom metallization is of a lesser purity than a top metallization whereby the bottom metallization may be effectively soldered without leaching of the metal and the top metallization may be wire bonded. In an exemplary embodiment, the top metallization is essentially pure gold and the bottom metallization is an alloy of gold and platinum and/or palladium. The top and bottom metallizations are provided on a dielectric body that advantageously comprises a ceramic having a sintering temperature below the melting point of gold. In a further exemplary embodiment, the capacitance of the capacitor may be enhanced by providing one or more interior metallization planes parallel to the exterior metallizations and connected thereto by conductive vias.

Abstract: Very thin cast ceramic tape, preferably approximately 12 &mgr;m in thickness, is wrapped, preferably in a reversing spiral or helix, around a mandrel, preferably a mandrel made of steel and coated with a wax releasing agent, for so many times, preferably five or greater, as achieves a desired thickness of a tube wall, preferably about 100 &mgr;m. The green ceramic tube is then laminated in a pressure laminator, preferably a hydrostatic laminator at 3000 to 5000 psi, linking polymer chains between each ceramic layer, cross-linking polymer chains within each ceramic layer, and densifying the produced ceramic laminate tube by reducing porosity.

Abstract: Very thin cast ceramic tape, preferably approximately 12 &mgr;m in thickness, is wrapped, preferably in a reversing spiral or helix, around a mandrel, preferably a mandrel made of steel and coated with a wax releasing agent, for so many times, preferably five or greater, as achieves a desired thickness of a tube wall, preferably about 100 &mgr;m. The green ceramic tube is then laminated in a pressure laminator, preferably a hydrostatic laminator at 3000 to 5000 psi, linking polymer chains between each ceramic layer, cross-linking polymer chains within each ceramic layer, and densifying the produced ceramic laminate tube by reducing porosity.

Abstract: A ceramic capacitor typically 10 mils to 340 mils square by typically 4-20 mils thickness with areas of metallization, or pads, to which electrical connections may be made on, typically, each of two opposite exterior surfaces, has embedded at least one, and normally two or more, metallization planes at close, typically 0.5 mil, separation. Each interior metallization plane connects through multiple redundant vias, as are preferably made by (ii) punching, (ii) drilling, (iii) laser drilling, or (iv) radiation patterning of a green ceramic sheet having a photosensitive binder, to an associated surface pad or trace. The vias are both numerous and redundant, typically being of 2 mil diameter on 10 mil centers in a pin grid array pattern over and through entire ceramic layers of the capacitor, permitting both (i) easy fabrication without exacting alignment or registration between layers, and (ii) low Equivalent Series Resistance (ESR) in the finished capacitor.

Abstract: A ceramic electrical device or component, normally a barium titanate ceramic capacitor, having a first coefficient of thermal expansion (CTE), typically about 10 parts per million per degree centigrade (10 ppm/.degree.C.), is physically and electrically mounted through an intermediary solder layer, normally copper, to a lead frame, normally made from a selected alloy of nickel-iron, having a second CTE at least one-fifth (20%) less, and more typically about 5 ppm/.degree.C., or one-half (50%) less, than is the CTE of the ceramic capacitor. Because ceramics are stronger in compression than in tension, the ceramic capacitor held within the lead frame is less likely to undergo a stress fracture at temperatures elevated above those of assembly than would be the case should the CTE's be equal, or should the CTE of the lead frame be greater than the CTE of the ceramic capacitor.

Abstract: Variable width electrically conductive (i) traces and (ii) pads in the forms of castellations and connecting traces upon the surfaces of volume microminiature electronic components permit variable area electrical interconnection in three dimensions, particularly of monolithic, buried-substrate, multiple ceramic capacitors to integrated circuit receivers and amplifiers to make microminiature hearing aids insertable within the ear canal. A preferred embodiment monolithic multiple capacitor with side, top and bottom surfaces has a number of electrically conductive parallel layers disposed within its body with a conductive trace extending from each layer to be exposed upon a side surface.

Abstract: Metal, normally gold or platinum, is printed, and is adhered by a glass frit, on the top and/or bottom surfaces of a multi-layer laid-up green ceramic wafers containing typically up to 16 layers and 800+ separate devices, typically 800+ monolithic, buried-substrate, ceramic multiple capacitors. The wafer is diced, and the multiple ceramic capacitors each with its patterned surface metal are co-fired. The integrally formed, top and bottom surface, conduction traces connect similarly formed pads, typically disposed in a "pin-grid" pattern, to later-added side traces or conductive castellations that connect to the electrodes of multiple buried-substrate capacitors. The pads are precisely located, and extend over such ample areas, to support the stable surface mounting, and the reliable electrical connection of, diverse external electrical circuits and components.

Abstract: Leaded electrical circuits and components, typically receivers and amplifiers used in micro-miniature hearing aids, are closely physically mounted by their leads extending within laser-drilled through-holes, typically three such holes, to multiple buried-substrate capacitors within a monolithic ceramic multiple capacitor. Electrical connection to the leads does not transpire within the holes, but rather though soldered or like connection to conductive pads surrounding the holes and continuing first as circuit traces on the top of the monolith, and then as electrically-conductive trace or castellations on the sides of the monolith, until reaching electrodes of the buried-substrate capacitors patterned so as to be brought to side surfaces of the monolith. The direct electrical connection is normally to multiple plates of plural buried-substrate capacitors, typically including a relatively large, typically 1.0 .mu.farad, capacitor in electrical parallel with a smaller, typically 100 picofarads, capacitor.

Abstract: A monolithic, buried-substrate, ceramic multiple capacitor is laid up as multiple capacitors that are isolated, one to the next, by a dual-dielectric-constant, three-layer-laminate, isolation layer. Each isolation layer has and presents (i) an innermost layer of a low dielectric constant (low K) material, located between (ii) outer laminate layers of a high dielectric constant (high K) material. By such construction negative effects of the physio-chemical reaction (i) occurring at the boundary between the high-K and low-K layers, (ii) contaminating the high-K dielectric and lowering its K, and (iii) undesirably serving both to lower the capacitance of any (buried substrate) capacitor that makes use of the ("contaminated") high-K dielectric while increasing capacitor leakage current, are mitigated or avoided.

Abstract: A monolithic multiple ceramic capacitor is made by interspersing layers of green tape containing ceramic powder in a binder with printed layers of electrical conductors, then compressing the layers and heating them to sinter the ceramic powder. Edge connections link the conducting layers in predetermined patterns to provide external connections to the capacitors. Use of parasitic or stray capacitance between pairs of external terminals provides additional useful values of capacitance. Unwanted stray capacitance between adjacent terminals is reduced by making slots by saw cuts or the like in either the green tape or the sintered material. Unwanted stray capacitance between elements inside the capacitor is reduced by ground planes between layers of capacitors and by layers of ceramic materials having relatively low dielectric constants to separate layers of capacitors, to form exterior layers of insulating material, or both.