Abstract: Certain exemplary embodiments can comprise a system, which can comprise a module communicatively coupled to a programmable logic controller (PLC). The module can comprise a transmission circuit and/or a receiving circuit. The module can be adapted to communicate with the PLC via 8B/10B encoded frames. A frame of the 8B/10B encoded frames can comprise a plurality of ordered fields.

Abstract: Certain exemplary embodiments can comprise a system, which can comprise a module communicatively coupled to a programmable logic controller (PLC). The module can comprise a transmission circuit and/or a receiving circuit. The module can be adapted to communicate with the PLC via 8B/10B encoded frames. A frame of the 8B/10B encoded frames can comprise a plurality of ordered fields.

Abstract: Certain exemplary embodiments can provide a programmable logic controller, which can comprise a Reduced Instruction Set Computer (RISC) processor. The RISC processor can be adapted to, responsive to a received request to process a Boolean operation, execute a single processor data access instruction addressed to a region of a memory-mapped register corresponding to the Boolean operation.

Abstract: Certain exemplary embodiments can comprise a system, which can comprise a module communicatively coupled to a programmable logic controller (PLC). The module can comprise a transmission circuit and/or a receiving circuit. The module can be adapted to communicate with the PLC via 8B/10B encoded frames. A frame of the 8B/10B encoded frames can comprise a plurality of ordered fields.

Abstract: Certain exemplary embodiments can comprise a system, which can comprise a module communicatively coupled to a programmable logic controller (PLC). The module can comprise a transmission circuit and/or a receiving circuit. The module can be adapted to communicate with the PLC via 8B/10B encoded frames. A frame of the 8B/10B encoded frames can comprise a plurality of ordered fields.

Abstract: At least one exemplary embodiment of the present invention includes a method comprising obtaining a first frequency and a second frequency. The method also comprises creating a table of values comprising a plurality of target frequencies intermediate to the first and second pulse width corresponding to each of the target frequencies from the plurality of target frequencies. The method further comprises outputting at least a portion of the values to a motion device.

Abstract: At least one exemplary embodiment of to present invention includes a method comprising obtaining a first frequency and a second frequency. The method also comprises creating a table of values comprising a plurality of target frequencies intermediate to the first and second frequencies, the table of values also comprising a pulse width, a pulse count, and a differential pulse width corresponding to each of the target frequencies from the plurality of target frequencies. The method further comprises outputting at least a portion of the values to a motion device.

Abstract: At least one exemplary embodiment of the present invention includes a method comprising obtaining a first frequency and a second frequency. The method also comprises creating a table of values comprising a plurality of target frequencies intermediate to the first and second frequencies, the table of values also comprising a pulse width, a pulse count and a differential pulse width corresponding to each of the target frequencies from the plurality of target frequencies. The method further comprises outputting at least a portion of the values to a motion device.

Abstract: Certain exemplary embodiments can provide a programmable logic controller, which can comprise a Reduced Instruction Set Computer (RISC) processor. The RISC processor can be adapted to, responsive to a received request to process a Boolean operation, execute a single processor data access instruction addressed to a region of a memory-mapped register corresponding to the Boolean operation.

Abstract: Certain exemplary embodiments can comprise a system, which can comprise a module communicatively coupled to a programmable logic controller (PLC). The module can comprise a transmission circuit and/or a receiving circuit. The module can be adapted to communicate with the PLC via 8B/10B encoded frames. A frame of the 8B/10B encoded frames can comprise a plurality of ordered fields.

Abstract: Certain exemplary embodiments can comprise a system, which can comprise a module communicatively coupled to a programmable logic controller (PLC). The module can comprise a transmission circuit and/or a receiving circuit. The module can be adapted to communicate with the PLC via 8B/10B encoded frames. A frame of the 8B/10B encoded frames can comprise a plurality of ordered fields.

Abstract: Certain exemplary embodiments provide a method for producing pulsed outputs, comprising: automatically changing a first user-specified pulse frequency to a second pulse frequency; and automatically outputting a plurality of pulses from the programmable logic controller at frequencies varying between the first user-specified pulse frequency and the second pulse frequency according to a user-specified linear-time-rate variation.

Abstract: At least one exemplary embodiment of the present invention includes a method comprising obtaining a first frequency and a second frequency. The method also comprises creating a table of values comprising a plurality of target frequencies intermediate to the first and second frequencies, the table of values also comprising a pulse width, a pulse count, and a differential pulse width corresponding to each of the target frequencies from the plurality of target frequencies. The method further comprises outputting at least a portion of the values to a motion device.

Abstract: Certain exemplary embodiments comprise a system, comprising: an electrical isolator adapted to couple a processor of a programmable logic controller to a user load; a transistor adapted to provide switching of a control signal provided by the processor for the user load; a totem pole output coupling the electrical isolator and the transistor and adapted to switch a gate of the transistor; and a power supply adapted to provide a floating regulated DC voltage to the gate of the transistor.

Abstract: A communication interface responds to a communication protocol for interfacing a controller and any of a plurality of discrete I/O devices. Each discrete I/O device has a different configuration. The interface has a plurality of modes of operation to accommodate the discrete I/O devices. In a first mode of operation, the interface accommodates a first discrete I/O device wherein a plurality of input pins input signals from a particular discrete I/O and a plurality of output pins output signals to the particular discrete I/O device. In a second mode of operation, the interface accommodates a second discrete I/O device wherein the input pins form a bidirectional input/output port and the output pins form a control and address line for controlling the second discrete I/O device and other discrete I/O devices.

Abstract: At least one exemplary embodiment of the present invention includes a system comprising a modem adapted to be integrated into a programmable logic controller and adapted to facilitate communications with a main processor of the programmable logic controller via a communications medium. At least one exemplary embodiment of the present invention includes a method comprising receiving a message from a main processor of a programmable logic controller, modulating the message within the programmable logic controller, and transmitting the message via a communications network. At least one exemplary embodiment of the present invention includes a method comprising receiving a message at a programmable logic controller from a communications network, demodulating the message within the programmable logic controller, and delivering the message to a main processor of the programmable logic controller.

Abstract: At least one exemplary embodiment comprises a system comprising an arithmetic logic unit; a memory comprising a pre-computed table of target pulse widths, changes in pulse width, and pulse counts distributed according to a constrained semi-logarithmic distribution, the memory connected to the arithmetic logic unit via a pipeline mechanism; and a state machine adapted to load each of the target pulse widths and changes in pulse width from the memory into the arithmetic logic unit at pre-determined intervals of pulse count while maintaining control of a pulse width generated by the arithmetic logic unit.

Abstract: Certain exemplary embodiments provide a method for producing pulsed outputs, comprising: automatically changing a first user-specified pulse frequency to a second pulse frequency; and automatically outputting a plurality of pulses from the programmable logic controller at frequencies varying between the first user-specified pulse frequency and the second pulse frequency according to a user-specified linear-time-rate variation.

Abstract: A communication interface responds to a communication protocol for interfacing a controller and any of a plurality of discrete I/O devices. Each discrete I/O device has a different configuration. The interface has a plurality of modes of operation to accommodate the discrete I/O devices. In a first mode of operation, the interface accommodates a first discrete I/O device wherein a plurality of input pins input signals from a particular discrete I/O and a plurality of output pins output signals to the particular discrete I/O device. In a second mode of operation, the interface accommodates a second discrete I/O device wherein the input pins form a bidirectional input/output port and the output pins form a control and address line for controlling the second discrete I/O device and other discrete I/O devices.

Abstract: A communication interface responds to a communication protocol for interfacing a controller and any of a plurality of discrete I/O devices. Each discrete I/O device has a different configuration. The interface has a plurality of modes of operation to accommodate the discrete I/O devices. In a first mode of operation, the interface accommodates a first discrete I/O device wherein a plurality of input pins input signals from a particular discrete I/O and a plurality of output pins output signals to the particular discrete I/O device. In a second mode of operation, the interface accommodates a second discrete I/O device wherein the input pins form a bidirectional input/output port and the output pins form a control and address line for controlling the second discrete I/O device and other discrete I/O devices.