Patents by Inventor Alan D. Raisanen

Alan D. Raisanen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7495347
    Abstract: A method that includes providing a semiconductor substrate having a mask on a surface thereof. The mask includes a first region having no masking elements and a second region having a plurality of masking elements. Each of the plurality of masking elements has a dimension that is equal to a first length, the first length less than twice a diffusion length of a dopant. The method further includes bombarding the semiconductor substrate and masking element with ions of the dopant. The ions form a first impurity concentration in the first region and a second impurity concentration in the second region.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: February 24, 2009
    Assignee: Xerox Corporation
    Inventors: Alan D. Raisanen, Shelby F. Nelson
  • Patent number: 6927153
    Abstract: A method that includes providing a semiconductor substrate having a mask on a surface thereof. The mask includes a first region having no masking elements and a second region having a plurality of masking elements. Each of the plurality of masking elements has a dimension that is equal to a first length, the first length less than twice a diffusion length of a dopant. The method further includes bombarding the semiconductor substrate and masking element with ions of the dopant. The ions form a first impurity concentration in the first region and a second impurity concentration in the second region.
    Type: Grant
    Filed: February 25, 2003
    Date of Patent: August 9, 2005
    Assignee: Xerox Corporation
    Inventors: Alan D. Raisanen, Shelby F. Nelson
  • Patent number: 6905196
    Abstract: A fluid ejector includes a fluid channel having a resistive heater and terminating in a nozzle, a common bus formed transverse to the fluid channel and between the resistive heater and the nozzle, a connection line laterally adjacent to the fluid channel, and a connection structure for electrically connecting the common bus with the resistive heater and the connection line, the connection structure including a first set of one or more layers for electrical connection and a second set of one or more layers for covering the common bus and connection line. The first set of one or more layers includes a doped polysilicon layer on or overlaid by an optional tantalum-silicide layer. The second set of one or more layers includes a nitride layer on or overlaid by a tantalum layer.
    Type: Grant
    Filed: May 8, 2003
    Date of Patent: June 14, 2005
    Assignee: Xerox Corporation
    Inventors: Scott N. Seabridge, Alan D. Raisanen, Scott C. Warner, Thomas A. Tellier, Cathie J. Burke, William G. Hawkins
  • Patent number: 6805433
    Abstract: A method of manufacturing a fluid ejection device having circular nozzles includes forming channels in a substrate, depositing a sacrificial material, such as photoresist, into channels to form a mold for the fluid channels and a fluid reservoir and then forming the remainder of the fluid ejection device above the sacrificial material on the substrate. Various novel fluid heater structures and an in situ fluid filter may be formed during the manufacturing process. The fluid ejection device can include a heater element located in the fluid chamber behind the nozzle opening. The geometry of the heating element can be planar. Alternatively, the heating element can be located inside the channel in either a half-cylindrical or fully-cylindrical configuration. The internal fluid pathways remain protected from contaminants by the sacrificial material. After all layers and manufacturing processes are complete, individual fluid ejection devices are diced and the sacrificial material is removed.
    Type: Grant
    Filed: May 19, 2003
    Date of Patent: October 19, 2004
    Assignee: Xerox Corporation
    Inventors: Alan D Raisanen, Shelby F Nelson
  • Publication number: 20040164379
    Abstract: A method that includes providing a semiconductor substrate having a mask on a surface thereof. The mask includes a first region having no masking elements and a second region having a plurality of masking elements. Each of the plurality of masking elements has a dimension that is equal to a first length, the first length less than twice a diffusion length of a dopant. The method further includes bombarding the semiconductor substrate and masking element with ions of the dopant. The ions form a first impurity concentration in the first region and a second impurity concentration in the second region.
    Type: Application
    Filed: February 25, 2003
    Publication date: August 26, 2004
    Applicant: Xerox Corporation
    Inventors: Alan D. Raisanen, Shelby F. Nelson
  • Patent number: 6767082
    Abstract: A variable geometry fluid ejection system can be used to minimize a separation between a main drop and satellite drop on a recording medium in a bi-directional fluid ejection system. The geometry of the fluid ejection system is varied by placing an actuator in an ejector nozzle to selectively vary the geometry of the nozzle between opposing directions of motion of the fluid ejection system across a recording medium, thereby maintaining a constant distance of main drop satellite drop separation between the opposing directions of motion.
    Type: Grant
    Filed: June 9, 2003
    Date of Patent: July 27, 2004
    Assignee: Xerox Corporation
    Inventor: Alan D Raisanen
  • Publication number: 20030210301
    Abstract: A fluid ejector includes a fluid channel having a resistive heater and terminating in a nozzle, a common bus formed transverse to the fluid channel and between the resistive heater and the nozzle, a connection line laterally adjacent to the fluid channel, and a connection structure for electrically connecting the common bus with the reistive heater and the connection line, the connection structure including a first set of one or more layers for electrical connection and a second set of one or more layers for covering the common bus and connection line. The first set of one or more layers includes a doped polysilicon layer on or overlaid by an optional tantalum-silicide layer. The second set of one or more layers includes a nitride layer on or overlaid by a tantalum layer.
    Type: Application
    Filed: May 8, 2003
    Publication date: November 13, 2003
    Applicant: XEROX CORPORATION
    Inventors: Scott N. Seabridge, Alan D. Raisanen, Scott C. Warner, Thomas A. Tellier, Cathie J. Burke, William G. Hawkins
  • Publication number: 20030089953
    Abstract: The present disclosure relates that by modifying the masking layer normally utilized for complimentary type tub development to provide one or more additional openings arranged in close proximity to the drain area of a selected power device of the non-complimentary type, that the dopant profile may be modified to provide a greater voltage breakdown exclusively for that selected power device without affecting similar type logic circuit non-complimentary devices as found within the same integrated circuit chip. Furthermore, this is accomplished without the need for providing an additional mask or additional process steps to supplement and thereby disturb a given predefined process set for the fabrication of semiconductor devices.
    Type: Application
    Filed: May 23, 2002
    Publication date: May 15, 2003
    Applicant: Xerox Corporation
    Inventors: Shelby F. Nelson, Alan D. Raisanen
  • Publication number: 20030089952
    Abstract: The present disclosure relates that by modifying the masking layer normally utilized for complimentary type tub development to provide one or more additional openings arranged in close proximity to the drain area of a selected power device of the non-complimentary type, that the dopant profile may be modified to provide a greater voltage breakdown exclusively for that selected power device without affecting similar type logic circuit non-complimentary devices as found within the same integrated circuit chip. Furthermore, this is accomplished without the need for providing an additional mask or additional process steps to supplement and thereby disturb a given predefined process set for the fabrication of semiconductor devices.
    Type: Application
    Filed: November 13, 2001
    Publication date: May 15, 2003
    Applicant: Xerox Corporation.
    Inventors: Shelby F. Nelson, Alan D. Raisanen
  • Patent number: 6227657
    Abstract: The systems and methods of this invention allows for an electrical contact structure of the drop ejecting transducer in an inkjet printhead to be designed in such a way that the relatively thick electrical contact lines are not in the ink drop ejection path between the drop ejector transducer and the corresponding nozzle. Such a design thereby minimizes any visible defects due to misdirected satellite drops.
    Type: Grant
    Filed: June 19, 2000
    Date of Patent: May 8, 2001
    Assignee: Xerox Corporation
    Inventors: Alan D. Raisanen, Cathie J. Burke, Eduardo Mariano Freire, Yonglin Xie, Dale R. Ims, Michael P. O'Horo, Scott C. Warner, Thomas A. Tellier, Scott N. Seabridge, William G. Hawkins
  • Patent number: 6146914
    Abstract: An improved method is disclosed for forming heater elements for an ink jet printhead. The resistance is more closely controlled by doping a central heater region which is formed relatively thinner than the heavily doped heater regions which are used as the gate and contact areas. The thinner central region can doped relatively heavy in order to more accurately adjust the heater resistance.In another embodiment, the thin layer is amorphous silicon rather than the polysilicon to increase the latitude of the energy input.
    Type: Grant
    Filed: December 7, 1998
    Date of Patent: November 14, 2000
    Assignee: Xerox Corporation
    Inventors: Cathie J. Burke, Alan D. Raisanen, Sean D. O'Brien
  • Patent number: 6109733
    Abstract: The efficiency of a thermal ink jet printhead is improved by providing a thermally grown field oxide layer and a deposited oxide layer, the two combined layers providing thermal insulation between a resistor layer and a silicon substrate. In a preferred embodiment, zirconium diboride is sputtered in the presence of oxygen to form a thin field oxide layer on a field oxide layer grown on the surface of the silicon substrate. At a predetermined time, during the sputtering process, oxygen is removed and the sputtering continues to form a conductive ZrB.sub.2 layer. The combined thickness of the two oxide layers provides the required thermal isolation between silicon substrate and heater resistor while the thermally grown field oxide layer enables the closer packing of resistor transistor drive circuits.
    Type: Grant
    Filed: November 21, 1997
    Date of Patent: August 29, 2000
    Assignee: Xerox Corporation
    Inventors: Alan D. Raisanen, Cathie J. Burke
  • Patent number: 6013160
    Abstract: The nucleation efficiency of a thermal ink jet printhead is improved by providing a heater resistor with a thin planar oxide film formed over a conductive heater resistive layer. In a preferred embodiment, zirconium diboride is sputtered onto a silicon substrate surface to form a first, electrically conductive base portion of the resistor. At a predetermined time, during the sputtering process, oxygen is introduced to form a thin film of ZrB.sub.2 O.sub.x. The surface of this film is very smooth having a surface roughness of <5 nm RMS.
    Type: Grant
    Filed: November 21, 1997
    Date of Patent: January 11, 2000
    Assignee: Xerox Corporation
    Inventors: Alan D. Raisanen, Cathie J. Burke
  • Patent number: 5980025
    Abstract: A thermal ink jet printhead is improved by providing a heater resistor which is mechanically isolated from overlying nitride and tantalum layers by growing a thin buffer oxide layer on the surface of the resistor heater layer. The introduction of the buffer oxide layer permits a thinner nitride layer which, in turn, reduces electrical resistance changes which would otherwise be introduced into the resistor arrays by mechanical stress after the nitride layer is deposited.
    Type: Grant
    Filed: November 21, 1997
    Date of Patent: November 9, 1999
    Assignee: Xerox Corporation
    Inventors: Cathie J. Burke, Alan D. Raisanen
  • Patent number: 5943076
    Abstract: The nucleation efficiency of a thermal ink jet printhead is improved by forming a heater element with a planar surface. A heater resistor, polysilicon in a preferred embodiment, has an irregular surface which can trap gas or vapors in the cracks or crevices. When the heater resistor is pulsed, the nucleation temperature is reduced by these trapped vapors requiring an increase in electrical input to the resistors, thereby reducing efficiency. The invention recognizes that a heater resistor with a planar surface in contact with an ink layer results in a higher nucleation temperature and increased efficiency. In one embodiment, a phosphosilicate glass (PSG) is flowed directly onto the resistor surface forming a planarization layer. Subsequent deposition of tantalum substantially replicates the underlying topography creating a heater resistor with a smooth surface adjacent the ink.
    Type: Grant
    Filed: February 24, 1997
    Date of Patent: August 24, 1999
    Assignee: Xerox Corporation
    Inventors: Cathie J. Burke, Michael P. O'Horo, Donald J. Drake, Alan D. Raisanen
  • Patent number: 5729261
    Abstract: An ink jet printhead has improved resistance to the corrosive effects of ink by coating the surface of a photo-imageable polymer with an ink resistant film. In one described embodiment, a thermal ink jet element is formed by bonding together a channel plate and a heater plate. Resistors and electrical connections are formed in the heater plate. A polyimide layer is formed so as to overlie the heater plate to protect the electrical elements while providing pit structure for the heater and for ink flow bypass. A tantalum film is formed on the surface of the polyimide layer to protect the layer from the effects of corrosive ink. In another embodiment, the ink resistant film is amorphous carbon or silicon nitride.
    Type: Grant
    Filed: March 28, 1996
    Date of Patent: March 17, 1998
    Assignee: Xerox Corporation
    Inventors: Cathie J. Burke, Daniel E. Kuhman, Daniel O. Roll, Alan D. Raisanen