Abstract: A method and apparatus are disclosed for allocating functional units in a multithreaded very large instruction word (VLIW) processor. The present invention combines the techniques of conventional very long instruction word architectures and conventional multithreaded architectures to reduce execution time within an individual program, as well as across a workload. The present invention utilizes instruction packet splitting to recover some efficiency lost with conventional multithreaded architectures. Instruction packet splitting allows an instruction bundle to be partially issued in one cycle, with the remainder of the bundle issued during a subsequent cycle. The allocation hardware assigns as many instructions from each packet as will fit on the available functional units, rather than allocating all instructions in an instruction packet at one time. Those instructions that cannot be allocated to a functional unit are retained in a ready-to-run register.

Abstract: A method and apparatus are disclosed for allocating functional units in a multithreaded very large instruction word (VLIW) processor. The present invention combines the techniques of conventional VLIW architectures and conventional multithreaded architectures to reduce execution time within an individual program, as well as across a workload. The present invention utilizes a compiler to detect parallelism. The disclosed multithreaded VLIW architecture exploits program parallelism by issuing multiple instructions, in a similar manner to single threaded VLIW processors, from a single program sequencer, and also supports multiple program sequencers, as in simultaneous multithreading. Instructions are allocated to functional units to issue multiple VLIW instructions to multiple functional units in the same cycle. The allocation mechanism of the present invention occupies a pipeline stage just before arguments are dispatched to functional units.

Abstract: The furniture piece facilitating wireless Local Area Network (LAN) access has a work surface and at least one support supporting the work surface. An antenna is disposed in one of the work surface and the support, and an access point is disposed in one of the work surface and the support.

Abstract: The furniture piece facilitating wireless Local Area Network (LAN) access has a work surface and at least one support supporting the work surface. An antenna is disposed in one of the work surface and the support, and an access point is disposed in one of the work surface and the support.

Abstract: A method and apparatus are disclosed for releasing functional units in a multithreaded very large instruction word (VLIW) processor. The functional unit release mechanism can retrieve the capacity lost due to multiple cycle instructions. The functional unit release mechanism of the present invention permits idle functional units to be reallocated to other threads, thereby improving workload efficiency. Instruction packets are assigned to functional units, which can maintain their state, independent of the issue logic. Each functional unit has an associated state machine (SM) that keeps track of the number of cycles that the functional unit will be occupied by a multiple-cycle instruction. Functional units do not reassign themselves as long as the functional unit is busy. When the instruction is complete, the functional unit can participate in functional unit allocation, even if other functional units assigned to the same thread are still busy.

Abstract: A method and apparatus are disclosed for allocating functional units in a multithreaded very large instruction word (VLIW) processor. The present invention combines the techniques of conventional very long instruction word (VLIW) architectures and conventional multithreaded architectures to reduce execution time within an individual program, as well as across a workload. The present invention utilizes instruction packet splitting to recover some efficiency lost with conventional multithreaded architectures. Instruction packet splitting allows an instruction bundle to be partially issued in one cycle, with the remainder of the bundle issued during a subsequent cycle. There are times, however, when instruction packets cannot be split without violating the semantics of the instruction packet assembled by the compiler. A packet split identification bit is disclosed that allows hardware to efficiently determine when it is permissible to split an instruction packet.

Abstract: Signaling information is communicated over an ATM link or other packet-based communication link using packet headers. The information may be, for example, telephony signaling information such as an on-hook/off-hook indicator, a ring/no-ring indicator, or any other type of information used in establishing, maintaining, terminating or otherwise configuring a telephony-based communication. In an illustrative embodiment, a single bit of signaling information is incorporated into a low order bit of a packet type indicator field in a header of an ATM user data cell. This low order bit, which is generally used as an End of Message (EOM) indicator in a cell which is part of a multi-cell message, can be used to transmit the signaling information in packets corresponding to single-cell messages.

Abstract: Line card control in an ATM or other packet-based switch is provided using an in-band device configuration in which control messages from a control processor of the switch are transmitted in one or more cells to a transmission convergence device in a line card. The transmission convergence device filters a stream of cells received in the line card in order to identify cells including control messages directed to the line card. The transmission convergence device then executes one or more commands associated with a given control message. Each control message may be transmitted in a single cell including a header and a payload. A message trailer portion of the payload may include device-specific data which specifies an interpretation of the payload structure. For example, the payload may include a series of commands, each including a read or write opcode, an address, and a data field.

Abstract: A history-based prefetch cache which includes a time queue. The time queue correlates past events with cache misses in a microprocessor. The time queue is set to N cycles, N being a predetermined, arbitrary or programmable amount. The prefetch cache is a prefetch target buffer which receives inputs from a time queue and a cache and determines if an event is present in the cache. If an address is not present in the cache it is prefetched based on past events and inserted into the prefetch target buffer so that the microprocessor will not miss it the next time.