Abstract: A method for writing data to memory that provides for generation of a predicate to disable a portion of the elements so that only the enabled elements are written to memory. Such a method may be employed to write multi-dimensional data to memory and/or may be used with a streaming address generator.

Abstract: A processor with instruction storage configured to store processor instructions, data storage configured to store processor data representing an array, the array including plural data elements, a controller, and an instruction pipeline. The instruction pipeline includes: a load stage circuit configured to load an array element from the data storage, a compare stage circuit configured to compare the array element to a reference value, a store stage circuit configured to store a set of results that includes a result of the comparison of the array element to the reference value, and a loop hit detect stage circuit configured to determine whether any of the set of results is associated with a hit on the reference value.

Abstract: An audio system has a speaker port defining a speaker port cavity, which has a speaker port outlet communicating acoustically with a user's ear canal. A speaker generates output sound in the speaker port cavity based on a speaker signal received at the speaker. The output sound travels along an acoustic path extending from the speaker through the speaker port outlet to an ear canal. A speaker port microphone in acoustic communication with the speaker port cavity produces a speaker port microphone signal in response to input sound. An analysis unit receives the speaker signal and the speaker port microphone signal, uses the speaker signal and the speaker port microphone signal to determine a change in acoustic properties of the acoustic path, and uses the determined change in acoustic properties of the acoustic path to determine a change in physical properties of the audio system along the acoustic path.

Abstract: Various embodiments of the present disclosure relate to conditional branch instructions to support software pipelining techniques. In an example embodiment, a system including instruction fetch circuitry, decoder circuitry, and conditional branch circuitry is provided. The instruction fetch circuitry is configured to fetch a conditional branch instruction from memory and provide the instruction to the decoder circuitry. The instruction includes an iteration count and multiple branch destinations. The branch destinations include two or more branch destinations corresponding to conditions against which the conditional branch circuitry evaluates the iteration count.

Abstract: A method for writing data to memory that provides for generation of a predicate to disable a portion of the elements so that only the enabled elements are written to memory. Such a method may be employed to write multi-dimensional data to memory and/or may be used with a streaming address generator.

Abstract: Various embodiments of the present disclosure relate to conditional branch instructions to support software pipelining techniques. In an example embodiment, a system including instruction fetch circuitry, decoder circuitry, and conditional branch circuitry is provided. The instruction fetch circuitry is configured to fetch a conditional branch instruction from memory and provide the instruction to the decoder circuitry. The instruction includes an iteration count and multiple branch destinations. The branch destinations include two or more branch destinations corresponding to conditions against which the conditional branch circuitry evaluates the iteration count.

Abstract: Various embodiments of the present disclosure relate to conditional branch instructions to support software pipelining techniques. In an example embodiment, a system including instruction fetch circuitry, decoder circuitry, and conditional branch circuitry is provided. The instruction fetch circuitry is configured to fetch a conditional branch instruction from memory and provide the instruction to the decoder circuitry. The instruction includes an iteration count and multiple branch destinations. The branch destinations include two or more branch destinations corresponding to conditions against which the conditional branch circuitry evaluates the iteration count.

Abstract: A hearing assistance system is disclosed that comprises a hearing assistance device configured to reproduce sounds and to assist a person to hear the sounds, the hearing assistance device including a left hearing assistance device and a right hearing assistance device, and a computing device in communication with the hearing assistance device. The computing device interacts with the hearing assistance device to implement a fitting mode wherein the hearing assistance device is caused to generate fitting sounds usable to evaluate whether the left and right hearing devices are properly fitted into respective left and right ears of the person. The computing device produces a communication indicative of whether the left and right hearing assistance devices are properly fitted into respective left and right ears of the person.

Abstract: A digital data processor includes an instruction memory storing instructions specifying data processing operations and a data operand field, an instruction decoder coupled to the instruction memory for recalling instructions from the instruction memory and determining the operation and the data operand, and an operational unit coupled to a data register file and an instruction decoder to perform an operation upon an operand corresponding to an instruction decoded by the instruction decoder and storing results of the operation. The operational unit is configured to perform a table recall in response to a look up table read instruction by recalling data elements from a specified location and adjacent location to the specified location, in a specified number of at least one table and storing the recalled data elements in successive slots in a destination register. Recalled data elements include at least one interpolated data element in the adjacent location.

Abstract: A processor with instruction storage configured to store processor instructions, data storage configured to store processor data representing an array, the array including plural data elements, a controller, and an instruction pipeline. The instruction pipeline includes: a load stage circuit configured to load an array element from the data storage, a compare stage circuit configured to compare the array element to a reference value, a store stage circuit configured to store a set of results that includes a result of the comparison of the array element to the reference value, and a loop hit detect stage circuit configured to determine whether any of the set of results is associated with a hit on the reference value.

Abstract: A digital data processor includes an instruction memory storing instructions specifying data processing operations and a data operand field, an instruction decoder coupled to the instruction memory for recalling instructions from the instruction memory and determining the operation and the data operand, and an operational unit coupled to a data register file and an instruction decoder to perform an operation upon an operand corresponding to an instruction decoded by the instruction decoder and storing results of the operation. The operational unit is configured to perform a table recall in response to a look up table read instruction by recalling data elements from a specified location and adjacent location to the specified location, in a specified number of at least one table and storing the recalled data elements in successive slots in a destination register. Recalled data elements include at least one interpolated data element in the adjacent location.

Abstract: A processor with instruction storage configured to store processor instructions, data storage configured to store processor data representing an array, the array including plural data elements, a controller, and an instruction pipeline. The instruction pipeline includes: a load stage circuit configured to load an array element from the data storage, a compare stage circuit configured to compare the array element to a reference value, a store stage circuit configured to store a set of results that includes a result of the comparison of the array element to the reference value, and a loop hit detect stage circuit configured to determine whether any of the set of results is associated with a hit on the reference value.

Abstract: An audio transmitter is disclosed that comprises at least one microphone configured to receive ambient audio and produce an ambient audio signal indicative of the received ambient audio, a pairing component arranged to facilitate pairing of the audio transmitter with a wireless audio reproducing device, and an audio transmission component arranged to wirelessly transmit a short-range audio signal to a paired wireless audio reproducing device. The short-range audio signal is usable by the wireless audio reproducing device to reproduce audio representative of the received ambient audio.

Abstract: A system for hot swapping a network switch without disconnecting the network switch connectors is provided. The system disaggregates the switch faceplate network cable connectors from the internal components of the network switch so that the internal switch components may be removed from the switch without disconnecting the switch network cables.

Abstract: An ear tip has an inner part connectable to an ear bud body of an earbud, and an outer part disposed at least partially over the inner part. The outer part is flexible and is for coupling the ear tip to a user's ear canal. The inner part includes an inwardly facing wall and an outwardly facing wall, the inner wall defining at least part of a primary sound communication path between the ear canal and the ear bud body. The inner part includes at least one tip vent that defines an ambient sound communication path between the inwardly facing wall and the outwardly facing wall, and thereby the user's ear canal and ambient. The inner part provides an acoustic impedance to sound passing through the at least one tip vent and thereby defined sound characteristics in the ambient audio communication path. An ear bud is also described.

Abstract: A hearing assistance system is disclosed that comprises a hearing assistance device configured to reproduce sounds and to assist a person to hear the sounds, the hearing assistance device including a left hearing assistance device and a right hearing assistance device, and a computing device in communication with the hearing assistance device. The computing device interacts with the hearing assistance device to implement a fitting mode wherein the hearing assistance device is caused to generate fitting sounds usable to evaluate whether the left and right hearing devices are properly fitted into respective left and right ears of the person. The computing device produces a communication indicative of whether the left and right hearing assistance devices are properly fitted into respective left and right ears of the person.

Abstract: A wellhead alignment system includes a visual marker configured to be placed at a wellhead and a camera configured to capture an image that includes the visual marker. The wellhead alignment system also includes one or more processors configured to apply computer vision algorithms to identify the visual marker in the image and to calculate an offset between the wellhead and a drilling rig based on a position of the visual marker in the image.

Abstract: A processor with instruction storage configured to store processor instructions, data storage configured to store processor data representing an array, the array including plural data elements, a controller, and an instruction pipeline. The instruction pipeline includes: a load stage circuit configured to load an array element from the data storage, a compare stage circuit configured to compare the array element to a reference value, a store stage circuit configured to store a set of results that includes a result of the comparison of the array element to the reference value, and a loop hit detect stage circuit configured to determine whether any of the set of results is associated with a hit on the reference value.

Abstract: A system is disclosed for configuring a hearing device. The system includes an audiogram processing component arranged to process image data indicative of an image of an audiogram associated with a person so as to produce audiogram data indicative of the audiogram, and a hearing device configuration component arranged to produce hearing device configuration data based on the audiogram data. The configuration data is indicative of configuration settings for a hearing device that will cause the hearing device to assist the hearing of the person.

Abstract: A digital data processor includes an instruction memory storing instructions each specifying a data processing operation and at least one data operand field, an instruction decoder coupled to the instruction memory for sequentially recalling instructions from the instruction memory and determining the data processing operation and the at least one data operand, and at least one operational unit coupled to a data register file and to an instruction decoder to perform a data processing operation upon at least one operand corresponding to an instruction decoded by the instruction decoder and storing results of the data processing operation. The operational unit is configured to increment histogram values in response to a histogram instruction by incrementing a bin entry at a specified location in a specified number of at least one histogram.