Abstract: A rail-to-rail-Input Buffer with constant mutual conductance includes a differential input; a first differential stage supplied with a first reference current; a second differential stage supplied with a second reference current; a switching PMOS-transistor which switches through when the input signal is higher than a first threshold voltage to divert the first reference current to a first current mirror circuit; a switching NMOS-transistor which switches through when an input signal is lower than a second threshold voltage to divert the second reference current to a second current mirror circuit; a third differential stage supplied with the mirrored first reference current and replaces the first differential stage when the input signal is higher than the first threshold voltage; and a fourth differential stage supplied with the mirrored second reference current and replaces the second differential stage when the input signal is lower than the second threshold voltage.

Abstract: Rail-to-rail-Input Buffer with constant mutual conductance comprising a differential input having a first input terminal and a second input terminal for applying an input signal; a first differential stage supplied with a first reference current, wherein the first differential stage is formed by PMOS-transistors having gate terminals connected to the input terminals; a second differential stage supplied with a second reference current wherein the second differential stage is formed by NMOS-transistors having gate terminals connected to the input terminals; a switching PMOS-transistor which switches through when the input signal is higher than a predetermined first threshold voltage to divert the first reference current supplied to the first differential stage to a first current mirror circuit which mirrors the first reference current; a switching NMOS-transistor which switches through when the input signal is lower than a predetermined second threshold voltage to divert the second reference current supplied t

Abstract: A switched capacitor anplifier circuit is provided with two independent reference voltages, one which provides an appropriate bias level for the amplifiers, and one which sets a common mode input level for the amplifiers, thereby allowing the dynamic range to be maximized.

Abstract: A switched capacitor amplifier circuit is provided with two independent reference voltages, one which provides an appropriate bias level for the amplifiers, and one which sets a common mode input level for the amplifiers, thereby allowing the dynamic range to be maximised.