Abstract: A synchronous DRAM (SDRAM) terminates a write operation in response to detecting deactivation of a data strobe signal applied to it during the write operation. In one example, the SDRAM comprises a buffer circuit and an early write termination circuit. The buffer circuit is configured to sample input data responsive to a data strobe signal applied to the SDRAM during a write operation and direct the input data to one or more memory cells of the SDRAM for storing the input data. The early write termination circuit is configured to terminate the write operation at less than a programmed burst length by disabling access to one or more of the memory cells after storage of the sampled input data responsive to detecting deactivation of the data strobe signal.

Abstract: A synchronous DRAM (SDRAM) terminates a write operation in response to detecting deactivation of a data strobe signal applied to it during the write operation. In one example, the SDRAM comprises a buffer circuit and an early write termination circuit. The buffer circuit is configured to sample input data responsive to a data strobe signal applied to the SDRAM during a write operation and direct the input data to one or more memory cells of the SDRAM for storing the input data. The early write termination circuit is configured to terminate the write operation at less than a programmed burst length by disabling access to one or more of the memory cells after storage of the sampled input data responsive to detecting deactivation of the data strobe signal.

Abstract: A memory includes a status register and a read/write data bus. The status register is configured to pass status register values to the read/write data bus in response to a status register read command.