Abstract: The present disclosure generally relates to navigating a collection of media items. In accordance with one embodiment, in response to receiving an input, a device displays a first view of a collection of media items, including concurrently displaying a representation of a first time period and a representation of a second time period. In accordance with a determination that a current time is associated with a first recurring temporal event: the representation of the first time period includes a first representative media item and the representation of the second time period includes a second representative media item. In accordance with a determination that the current time is associated with a second recurring temporal event, the representation of the first time period includes a third representative media item and the representation of the second time period includes a fourth representative media item.

Abstract: A system, method, apparatus and electronic control unit are provided for centralized data collection at a single controller device (110) in a distributed service-oriented system (100) by applying one or more classifiers (102-104, 114) to a message traffic packet (1) received at the Ethernet switch (101) of the single controller device to selectively identify service update information from service-oriented traffic messages in the message traffic packet without generating additional message traffic packets on the network system bus, and by mirroring each message traffic packet (3) containing service update information to a processing element (111) in the single controller to identify and extract specified data from the identified service update information for storage in a centralized database which is updated as services publish new information on the network system bus.

Abstract: A system, method, and apparatus are provided for processing packets received over Controller Area Network (CAN) interface where a CAN protocol controller computes a CRC value from header and payload values in a received CAN data frame to verify frame integrity of the received CAN data frame across a physical media layer, and then stores the header and payload values and the CRC value in a memory buffer of the CAN protocol controller so that a host core can compute a reconstructed CRC value from the header and payload values retrieved from the memory buffer, and then compare the reconstructed CRC value to the CRC value retrieved from the memory buffer to verify frame integrity of the received CAN data frame at a transaction layer.

Abstract: A system, method, and apparatus are provided for processing packets received over Controller Area Network (CAN) interface where a CAN protocol controller computes a CRC value from header and payload values in a received CAN data frame to verify frame integrity of the received CAN data frame across a physical media layer, and then stores the header and payload values and the CRC value in a memory buffer of the CAN protocol controller so that a host core can compute a reconstructed CRC value from the header and payload values retrieved from the memory buffer, and then compare the reconstructed CRC value to the CRC value retrieved from the memory buffer to verify frame integrity of the received CAN data frame at a transaction layer.

Abstract: A system, method, apparatus and electronic control unit are provided for centralized data collection at a single controller device (110) in a distributed service-oriented system (100) by applying one or more classifiers (102-104, 114) to a message traffic packet (1) received at the Ethernet switch (101) of the single controller device to selectively identify service update information from service-oriented traffic messages in the message traffic packet without generating additional message traffic packets on the network system bus, and by mirroring each message traffic packet (3) containing service update information to a processing element (111) in the single controller to identify and extract specified data from the identified service update information for storage in a centralized database which is updated as services publish new information on the network system bus.

Abstract: A system on chip, comprising a processing unit for executing processes, a memory unit, and a memory control unit connected between the processing unit and the memory unit, is described. The memory control unit allocates a memory region to a process. The memory control unit comprises a process activity counter which counts a duration of the process or transactions by the process to or from the memory region and which maintains a process activity count representing the counted duration of the process or the counted transactions to or from the memory region. The memory control unit disables the memory region in response to the process activity count exceeding a maximum process activity count. Notably, it blocks the memory region against further transactions by the process and against transactions by any other processes. A method of operating a system on chip is also described.

Abstract: A data processing device, comprising a processing unit and a test control unit connected to the processing unit, is described. The processing unit and the test control unit are arranged to: start a logic test of the processing unit; detect a test abort event; and, in response to the test abort event, perform an event response action which comprises aborting the logic test and booting the processing unit, said booting including executing an event handling routine. The event response action may comprise setting a reset vector to an address of the event handling routine. System availability may thus be improved. In particular, the delay between capturing an asynchronous signal and responding to it may be reduced. The test abort event may, for example, be an asynchronous event having certain pre-defined characteristics. A method of operating a data processing device is also described.

Abstract: Apparatus suitable for detecting a fault in a processor comprises a monitor which receives input and output signals from the processor and generates a hash index key which is used to access entries in a hash table. The entries may include actions such as setting a timer so that the response of an output to a change of state of an input may be confirmed as valid within a specified time interval.

Abstract: A method of controlling access by a master to a peripheral includes receiving an interrupt priority level from an interrupt controller associated with the peripheral, comparing the interrupt priority level with respective a pre-established interrupt access level to obtain an interrupt level comparison result, establishing whether an access condition is satisfied in dependence on the interrupt level comparison result, and if the access condition is satisfied, granting access. If the access condition is not satisfied, access is denied. Further, a circuitry is described including a master, a peripheral, and an access control circuitry including an interrupt controller associated with the peripheral. The access control circuitry is arranged to perform a method of controlling access by the master to the peripheral.

Abstract: A method of controlling direct memory access of a peripheral memory of a peripheral by a master is described. The method includes checking whether there is a pending request from the peripheral for a direct memory access service, establishing whether an access condition is satisfied in dependence on at least whether there is a pending request, and, if the access condition is satisfied, granting access to the master. Also, an associated device and an associated computer program product are described.

Abstract: A peripheral integrated circuit (IC) device for providing support to a data processing IC device. The peripheral IC device comprises a fault detection component arranged to detect an occurrence of fault conditions within the data processing IC device. The peripheral IC device further comprises a safe state control component. Upon detection of a fault condition occurring within the data processing IC device by the fault detection component, the safe state control component is arranged to cause at least one I/O cell of the data processing IC device to be configured into at least one scan-chain, and cause at least one predefined control signal to be scanned into the at least one scan-chain to configure the at least one I/O cell into a state corresponding to the predefined control signal.

Abstract: A data processing device, comprising a processing unit and a test control unit connected to the processing unit, is described. The processing unit and the test control unit are arranged to: start a logic test of the processing unit; detect a test abort event; and, in response to the test abort event, perform an event response action which comprises aborting the logic test and booting the processing unit, said booting including executing an event handling routine. The event response action may comprise setting a reset vector to an address of the event handling routine. System availability may thus be improved. In particular, the delay between capturing an asynchronous signal and responding to it may be reduced. The test abort event may, for example, be an asynchronous event having certain pre-defined characteristics. A method of operating a data processing device is also described.

Abstract: Apparatus suitable for detecting a fault in a processor comprises a monitor which receives input and output signals from the processor and generates a hash index key which is used to access entries in a hash table. The entries may include actions such as setting a timer so that the response of an output to a change of state of an input may be confirmed as valid within a specified time interval.

Abstract: A microcontroller operable in a high power mode and a low power unit (LPU) run mode includes primary and LPU domains, primary and LPU mode controllers, and primary and LPU clock generator modules. The primary domain includes a first set of circuits and a first set of cores. The LPU domain includes second and third sets of circuits, a second set of cores, and a switching module. In the high power mode, the switching module connects the first and second sets of cores to at least one of the first, second and third sets of circuits, while in the LPU run mode, the switching module isolates the LPU domain from the primary domain and activates a small microcontroller system (SMS) that includes the LPU domain, the LPU mode controller and the LPU clock generator module. The SMS has further low power modes within the LPU run mode.

Abstract: A method of controlling direct memory access of a peripheral memory of a peripheral by a master is described. The method includes checking whether there is a pending request from the peripheral for a direct memory access service, establishing whether an access condition is satisfied in dependence on at least whether there is a pending request, and, if the access condition is satisfied, granting access to the master. Also, an associated device and an associated computer program product are described.

Abstract: A peripheral integrated circuit (IC) device for providing support to a data processing IC device. The peripheral IC device comprises a fault detection component arranged to detect an occurrence of fault conditions within the data processing IC device. The peripheral IC device further comprises a safe state control component. Upon detection of a fault condition occurring within the data processing IC device by the fault detection component, the safe state control component is arranged to cause at least one I/O cell of the data processing IC device to be configured into at least one scan-chain, and cause at least one predefined control signal to be scanned into the at least one scan-chain to configure the at least one I/O cell into a state corresponding to the predefined control signal.

Abstract: A microcontroller operable in a high power mode and a low power unit (LPU) run mode includes primary and LPU domains, primary and LPU mode controllers, and primary and LPU clock generator modules. The primary domain includes a first set of circuits and a first set of cores. The LPU domain includes second and third sets of circuits, a second set of cores, and a switching module. In the high power mode, the switching module connects the first and second sets of cores to at least one of the first, second and third sets of circuits, while in the LPU run mode, the switching module isolates the LPU domain from the primary domain and activates a small microcontroller system (SMS) that includes the LPU domain, the LPU mode controller and the LPU clock generator module. The SMS has further low power modes within the LPU run mode.

Abstract: A method of controlling access by a master to a peripheral includes receiving one or more interrupt priority levels from one or more interrupt controllers associated with the peripheral, comparing the one or more interrupt priority level with respective one or more pre-established interrupt access levels to obtain an interrupt level comparison result, establishing whether an access condition is satisfied in dependence on at least the interrupt level comparison result, and if the access condition is satisfied, granting access. If the access condition is not satisfied, access is denied. Further, a circuitry is described including one or more masters, one or more peripherals, and an access control circuitry including one or more interrupt controllers associated with the one or more peripherals. The access control circuitry is arranged to perform a method of controlling access by a master of the one or more masters to a peripheral of the one or more peripherals.

Abstract: A power management system permits a small microcontroller subsystem or low power domain to continuously operate while a main subsystem domain is cycling from power on to off. The power management system supports asynchronous domains with common shared peripherals. The asynchronous domains operate as a single entity while in a full power mode with the peripheral and system resources being shared. The system can be used in automotive systems where most of the system is power-gated leaving just a power regulator controller, some counters and an input/output segment alive for wakeup purposes.