Abstract: A distributed power management system is configured determine a node power consumption of a node during a first time interval. The system can determine a node power cap. The system can determine a proportional component power budget for a component of the node based, at least in part, on the node power consumption and a component power consumption. The system can determine a power budget for the component for a second time interval based, at least in part on the proportional component power budget.

Abstract: A distributed power management system is configured determine a node power consumption of a node during a first time interval. The system can determine a node power cap. The system can determine a proportional component power budget for a component of the node based, at least in part, on the node power consumption and a component power consumption. The system can determine a power budget for the component for a second time interval based, at least in part on the proportional component power budget.

Abstract: A distributed power management system is configured determine a node power consumption of a node during a first time interval. The system can determine a node power cap. The system can determine a proportional component power budget for a component of the node based, at least in part, on the node power consumption and a component power consumption. The system can determine a power budget for the component for a second time interval based, at least in part on the proportional component power budget.

Abstract: A multi-phase buck converter comprises a first comparator, a second comparator and a counter. The first comparator has a first node connected to a first voltage reference and a second node. The second comparator has a first node connected to a second voltage reference and a second node. The second node of the second comparator and the second node of the first comparator are together connected to an input voltage from an active phase of the buck converter. The counter is configured to adjust a number of active phases of the buck converter based on the input voltage.

Abstract: The present disclosure relates to voltage regulation techniques. In some embodiments, a voltage regulator is configured to regulate an output voltage based on a reference voltage. The voltage regulator comprises an analog-to-digital converter, an encoder, a decoder and a power stage. The analog-to-digital converter receives the reference voltage and an output voltage of the voltage regulator and provides a digital error signal. The encoder is coupled to the analog-to-digital converter output and configured to provide a multi-bit digital control signal based upon a present value of the digital error signal, a plurality of pre-determined coefficients, and a plurality of previous values of the digital error signal. The decoder is coupled to the encoder and configured to generate a plurality of control signals based on the multi-bit digital control signal. The power stage comprises a plurality of power cells which are coupled to a power supply and which receive the plurality of control signals, respectively.

Abstract: A multi-phase buck converter comprises a first comparator, a second comparator and a counter. The first comparator has a first node connected to a first voltage reference and a second node. The second comparator has a first node connected to a second voltage reference and a second node. The second node of the second comparator and the second node of the first comparator are together connected to an input voltage from an active phase of the buck converter. The counter is configured to adjust a number of active phases of the buck converter based on the input voltage.

Abstract: The present disclosure relates to voltage regulation techniques. In some embodiments, a voltage regulator is configured to regulate an output voltage based on a reference voltage. The voltage regulator comprises an analog-to-digital converter, an encoder, a decoder and a power stage. The analog-to-digital converter receives the reference voltage and an output voltage of the voltage regulator and provides a digital error signal. The encoder is coupled to the analog-to-digital converter output and configured to provide a multi-bit digital control signal based upon a present value of the digital error signal, a plurality of pre-determined coefficients, and a plurality of previous values of the digital error signal. The decoder is coupled to the encoder and configured to generate a plurality of control signals based on the multi-bit digital control signal. The power stage comprises a plurality of power cells which are coupled to a power supply and which receive the plurality of control signals, respectively.

Abstract: A distributed power management system is configured determine a node power consumption of a node during a first time interval. The system can determine a node power cap. The system can determine a proportional component power budget for a component of the node based, at least in part, on the node power consumption and a component power consumption. The system can determine a power budget for the component for a second time interval based, at least in part on the proportional component power budget.

Abstract: A distributed power management computer program product is configured to collect power consumption data that indicates power consumption by at least a plurality of the components of a node. The program code can be configured to provide, to each of a plurality of controllers associated with a respective one of the plurality of components, the power consumption data. The program code can be configured to determine a node power consumption. The program code can be configured to determine a power differential as a difference between the node power consumption and an upper power consumption threshold of the node. The program code can be configured to determine a proportion of the node power consumption consumed by a first component. The program code can be configured to compute a local power budget for the first component.

Abstract: Embodiments include collecting, from each of a plurality of controllers of a node having a plurality of components, component power consumption. Each of the plurality of controllers is associated with one or more of the components. The component power consumptions are provided to the controllers. A node power consumption for the node is determined based, at least in part, on the component power consumption. The power cap is determined for the plurality of components. A power differential power is determined as a difference between the node power consumption and the power cap for the plurality of components. A proportion of the node power consumption consumed by the component is determined based on the component power consumption of the component. A local power budget is computed for the component based, at least in part, on the power differential and the proportion of the node power consumption consumed by the component.

Abstract: Embodiments include collecting, from each of a plurality of controllers of a node having a plurality of components, component power consumption. Each of the plurality of controllers is associated with one or more of the components. The component power consumptions are provided to the controllers. A node power consumption for the node is determined based, at least in part, on the component power consumption. The power cap is determined for the plurality of components. A power differential power is determined as a difference between the node power consumption and the power cap for the plurality of components. A proportion of the node power consumption consumed by the component is determined based on the component power consumption of the component. A local power budget is computed for the component based, at least in part, on the power differential and the proportion of the node power consumption consumed by the component.

Abstract: Described is an integrated circuit having a clock distribution network capable of transitioning from a non-resonant clock mode to a first resonant clock mode Transitions between clock modes or between various resonant clock frequencies are done gradually over a series of clock cycles. In example, when transitioning from a non-resonant clock mode to a first resonant clock mode, a strength of a clock sector driver is reduced over a series of clock cycles, and individual ones of a plurality of resonant switches associated with resonant circuits are modified in coordination with reducing the strength of the clock sector driver.

Abstract: A distributed power management computer program product is configured to collect power consumption data that indicates power consumption by at least a plurality of the components of a node. The program code can be configured to provide, to each of a plurality of controllers associated with a respective one of the plurality of components, the power consumption data. The program code can be configured to determine a node power consumption. The program code can be configured to determine a power differential as a difference between the node power consumption and an upper power consumption threshold of the node. The program code can be configured to determine a proportion of the node power consumption consumed by a first component. The program code can be configured to compute a local power budget for the first component.

Abstract: Described is an integrated circuit having a clock distribution network capable of transitioning from a non-resonant clock mode to a first resonant clock mode Transitions between clock modes or between various resonant clock frequencies are done gradually over a series of clock cycles. In example, when transitioning from a non-resonant clock mode to a first resonant clock mode, a strength of a clock sector driver is reduced over a series of clock cycles, and individual ones of a plurality of resonant switches associated with resonant circuits are modified in coordination with reducing the strength of the clock sector driver.

Abstract: In accordance with a first aspect of the present invention, an aircraft having a scramjet engine is provided. The scramjet engine includes a flowpath which varies in three dimensions. In accordance with a second aspect of the present invention, a method for launching an aircraft having a scramjet engine with a nozzle section and a solid rocket booster positioned within the nozzle section is provided. The method includes the steps of igniting the solid rocket booster to accelerate the aircraft to a speed at which the scramjet engine can operate, clearing the nozzle section by ejecting the solid rocket booster from the nozzle section upon exhaustion of the solid rocket booster; and injecting fuel into a flow of air passing through the scramjet engine and igniting the fuel and the air to provide thrust to the aircraft.

Abstract: An inverting circuit comprises a first inverter in a main path having a first input and a common ouput. A second inverter receives the first input and is coupled with a first voltage controlled pass gate to the common output. A third inverter couples a second input to the common output using a second voltage controlled pass gate. A fourth inverter couples the second input to the common output using the first voltage controlled pass gate. A ring oscillator is formed using a number N of the inverting circuits with each common output coupled to the first inputs forming a main ring of a ring oscillator. The second inputs are coupled to feed-forward signals from selected outputs. The resulting signals at the common outputs are an interpolation of the first and second input signals modulated by a control voltage coupled to the first and second pass gates.

Abstract: A scanned value is stored by loading the value into at least three latch stages, generating an output value based on a majority of the latch stage outputs, and feeding the output value back to the inputs of the latch stages to reload the latch stages with the latch circuit output value. Refreshing of the latch stages in this manner repairs any upset latch stage and restores the latch circuit to its original scanned state. The latch circuit may be repeatedly refreshed, preferably on a periodic basis, to prevent failures arising from multiple upsets. The feedback path may include a front-end multiplexer which receives the scan-in line and the output of the majority gate. Control logic selects the output value from the majority gate to pass to the latch stages during the refresh phase. The latch stages may be arranged in a master-slave configuration with a check stage at the slave level. The method is particularly suited for self-correcting scan latches of a microprocessor control system.

Abstract: A latch circuit having three latch stages generates a majority output value from the stages, senses when the latch stage outputs are not all equal, and feeds the majority output value back to inputs of the latch stages to reload the latch stages. The latch circuit uses a not-equal gate whose output is an error signal that can be monitored to determine when a single-event upset has occurred. A master stage is controlled by a first multiplexer which receives one system clock signal, while a slave stage is controlled by a second multiplexer which receives another system clock signal, and the latch stage outputs are connected to respective inputs of the not-equal gate, whose output is connected to second inputs of the multiplexers. The latch circuit is part of a latch control system, and reloading of the latch stages takes less than one cycle of the system clock (less than 500 picoseconds).

Abstract: An inverting circuit comprises a first inverter in a main path having a first input and a common ouput. A second inverter receives the first input and is coupled with a first voltage controlled pass gate to the common output. A third inverter couples a second input to the common output using a second voltage controlled pass gate. A fourth inverter couples the second input to the common output using the first voltage controlled pass gate. A ring oscillator is formed using a number N of the inverting circuits with each common output coupled to the first inputs forming a main ring of a ring oscillator. The second inputs are coupled to feed-forward signals from selected outputs. The resulting signals at the common outputs are an interpolation of the first and second input signals modulated by a control voltage coupled to the first and second pass gates.

Abstract: In accordance with a first aspect of the present invention, an aircraft having a scramjet engine is provided. The scramjet engine includes a flowpath which varies in three dimensions. In accordance with a second aspect of the present invention, a method for launching an aircraft having a scramjet engine with a nozzle section and a solid rocket booster positioned within the nozzle section is provided. The method includes the steps of igniting the solid rocket booster to accelerate the aircraft to a speed at which the scramjet engine can operate, clearing the nozzle section by ejecting the solid rocket booster from the nozzle section upon exhaustion of the solid rocket booster; and injecting fuel into a flow of air passing through the scramjet engine and igniting the fuel and the air to provide thrust to the aircraft.