Patents by Inventor Alan Elbanhawy
Alan Elbanhawy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8936985Abstract: A method can include forming a drift region, forming a well region above the drift region, and forming an active trench extending through the well region and into the drift region. The method can include forming a first source region in contact with a first sidewall of the active trench and a second source region in contact with a second sidewall of the active trench. The method also includes forming a charge control trench where the charge control trench is aligned parallel to the active trench and laterally separated from the active trench by a mesa region, and where the portion of the well region is in contact with the charge control trench and excludes any source region. The method also includes forming an oxide along a bottom of the active trench having a thickness greater than a thickness of an oxide along the first sidewall of the active trench.Type: GrantFiled: March 12, 2012Date of Patent: January 20, 2015Assignee: Fairchild Semiconductor CorporationInventors: Ashok Challa, Alan Elbanhawy, Dean E. Probst, Steven P. Sapp, Peter H. Wilson, Babak S. Sani, Becky Losee, Robert Herrick, James J. Murphy, Gordon K. Madson, Bruce D. Marchant, Christopher B. Kocon, Debra S. Woolsey
-
Publication number: 20120220091Abstract: A method for forming thick oxide at the bottom of a trench formed in a semiconductor substrate includes forming a conformal oxide film by a sub-atmospheric chemical vapor deposition process that fills the trench and covers a top surface of the substrate. The method also includes etching the oxide film off the top surface of the substrate and inside the trench to leave a substantially flat layer of oxide having a target thickness at the bottom of the trench.Type: ApplicationFiled: March 12, 2012Publication date: August 30, 2012Inventors: Ashok Challa, Alan Elbanhawy, Thomas E. Grebs, Nathan L. Kraft, Dean E. Probst, Rodney S. Ridley, Steven P. Sapp, Qi Wang, Chongman Yun, J.G. Lee, Peter H. Wilson, Joseph A. Yedinak, J.Y. Jung, H.C. Jang, Babak S. Sani, Richard Stokes, Gary M. Dolny, John Mytych, Becky Losee, Adam Selsley, Robert Herrick, James J. Murphy, Gordon K. Madson, Bruce D. Marchant, Christopher L. Rexer, Christopher B. Kocon, Debra S. Woolsey
-
Patent number: 8143124Abstract: A method of manufacturing a semiconductor device having a charge control trench and an active control trench with a thick oxide bottom includes forming a drift region, a well region extending above the drift region, an active trench extending through the well region and into the drift region, a charge control trench extending deeper into the drift region than the active trench, an oxide film that fills the active trench, the charge control trench and covers a top surface of the substrate, an electrode in the active trench, and source regions. The method also includes etching the oxide film off the top surface of the substrate and inside the active trench to leave a substantially flat layer of thick oxide having a target thickness at the bottom of the active trench.Type: GrantFiled: February 15, 2008Date of Patent: March 27, 2012Assignee: Fairchild Semiconductor CorporationInventors: Ashok Challa, Alan Elbanhawy, Dean E. Probst, Steven P. Sapp, Peter H. Wilson, Babak S. Sani, Becky Losee, Robert Herrick, James J. Murphy, Gordon K. Madson, Bruce D. Marchant, Christopher B. Kocon, Debra S. Woolsey
-
Patent number: 7982265Abstract: A semiconductor power device includes a drift region of a first conductivity type, a well region extending above the drift region and having a second conductivity type opposite the first conductivity type, an active trench extending through the well region and into the drift region. The active trench, which includes sidewalls and bottom lined with dielectric material, is substantially filled with a first conductive layer and a second conductive layer. The second conductive layer forms a gate electrode and is disposed above the first conductive layer and is separated from the first conductive layer by an inter-electrode dielectric material. The device also includes source regions having the first conductivity type formed inside the well region and adjacent the active trench and a charge control trench that extends deeper into the drift region than the active trench and is substantially filled with material to allow for vertical charge control in the drift region.Type: GrantFiled: January 22, 2008Date of Patent: July 19, 2011Assignee: Fairchild Semiconductor CorporationInventors: Ashok Challa, Alan Elbanhawy, Steven P. Sapp, Peter H. Wilson, Babak S. Sani, Christopher B. Kocon
-
Patent number: 7875498Abstract: A chip module is disclosed. It includes a circuit substrate, a semiconductor die comprising a power transistor mounted on the circuit substrate, and a passive electronic component. The passive electronic component is in electrical communication with the semiconductor die, and is in thermal communication with the semiconductor die.Type: GrantFiled: December 14, 2009Date of Patent: January 25, 2011Assignee: Fairchild Semiconductor CorporationInventors: Alan Elbanhawy, Benny Tjia
-
Patent number: 7872883Abstract: In one embodiment, a power converter system includes a switching circuitry having a plurality of switches operable to be turned on and off to cause current to flow to deliver power to a load. A driver circuitry is responsive to an oscillation signal and generates control signals for turning on and off the switches in the switching circuitry. A free-running oscillator circuitry provides the oscillation signal to the driver circuitry. The free-running oscillator circuitry has an operational amplifier. A frequency of the oscillation signal will be higher if the operational amplifier outputs a first value, and the frequency of the oscillation signal will be lower if the operational amplifier outputs a second value.Type: GrantFiled: January 29, 2008Date of Patent: January 18, 2011Assignee: Fairchild Semiconductor CorporationInventor: Alan Elbanhawy
-
Publication number: 20100093132Abstract: A chip module is disclosed. It includes a circuit substrate, a semiconductor die comprising a power transistor mounted on the circuit substrate, and a passive electronic component. The passive electronic component is in electrical communication with the semiconductor die, and is in thermal communication with the semiconductor die.Type: ApplicationFiled: December 14, 2009Publication date: April 15, 2010Inventors: Alan Elbanhawy, Benny Tjia
-
Patent number: 7656024Abstract: A chip module is disclosed. It includes a circuit substrate, a semiconductor die comprising a power transistor mounted on the circuit substrate, and a passive electronic component. The passive electronic component is in electrical communication with the semiconductor die, and is in thermal communication with the semiconductor die.Type: GrantFiled: June 30, 2006Date of Patent: February 2, 2010Assignee: Fairchild Semiconductor CorporationInventors: Alan Elbanhawy, Benny Tjia
-
Publication number: 20080197407Abstract: A method for controlling the thickness of an expitaxially grown semiconductor material includes providing a semiconductor substrate that is doped by dopants of a first type; forming a buffer layer atop the semiconductor substrate, the buffer layer being doped with dopants of a second type that has much less diffusivity relative to that of dopants of the first type and forming the expitaxially grown layer atop the buffer layer to a desired thickness. The buffer layer, which acts to counter an up-diffusion of the dopants of the first type from the substrate into the epitaxially grown layer, can be doped with arsenic or carbon or both arsenic and carbon. A semiconductor device includes the buffer layer to counter an up-diffusion of the dopants of the first type from the substrate into the epitaxially grown layer.Type: ApplicationFiled: February 28, 2008Publication date: August 21, 2008Inventors: Ashok Challa, Alan Elbanhawy, Steven P. Sapp, Qi Wang, Peter H. Wilson, Babak S. Sani, Christopher B. Kocon
-
Publication number: 20080150020Abstract: A semiconductor power device includes a drift region of a first conductivity type, a well region extending above the drift region and having a second conductivity type opposite the first conductivity type, an active trench extending through the well region and into the drift region. The active trench, which includes sidewalls and bottom lined with dielectric material, is substantially filled with a first conductive layer and a second conductive layer. The second conductive layer forms a gate electrode and is disposed above the first conductive layer and is separated from the first conductive layer by an inter-electrode dielectric material. The device also includes source regions having the first conductivity type formed inside the well region and adjacent the active trench and a charge control trench that extends deeper into the drift region than the active trench and is substantially filled with material to allow for vertical charge control in the drift region.Type: ApplicationFiled: January 22, 2008Publication date: June 26, 2008Inventors: Ashok Challa, Alan Elbanhawy, Thomas E. Grebs, Nathan L. Kraft, Dean E. Probst, Rodney S. Ridley, Steven P. Sapp, Qi Wang, Chongman Yun, J. G. Lee, Peter H. Wilson, Joseph A. Yedinak, J. Y. Jung, H. C. Jang, Babak S. Sani, Richard Stokes, Gary M. Dolny, John Mytych, Becky Losee, Adam Selsley, Robert Herrick, James J. Murphy, Gordon K. Madson, Bruce D. Marchant, Christopher L. Rexer, Christopher B. Kocon, Debra S. Woolsey
-
Publication number: 20080138953Abstract: A method for forming thick oxide at the bottom of a trench formed in a semiconductor substrate includes forming a conformal oxide film that fills the trench and covers a top surface of the substrate. and etching the oxide film off the top surface of the substrate and inside the trench to leave a substantially flat layer of oxide having a target thickness at the bottom of the trench. The oxide film can be deposited by sub-atmospheric chemical vapor deposition processes, directional Tetraethoxysilate (TEOS) processes, or high density plasma deposition processes that form a thicker oxide at the bottom of the trench than on the sidewalls of the trench.Type: ApplicationFiled: February 15, 2008Publication date: June 12, 2008Inventors: Ashok Challa, Alan Elbanhawy, Dean E. Probst, Steven P. Sapp, Peter H. Wilson, Babak S. Sani, Becky Losee, Robert Herrick, James J. Murphy, Gordon K. Madson, Bruce D. Marchant, Christopher B. Kocon, Debra S. Woolsey
-
Publication number: 20080135931Abstract: A semiconductor power device includes a drift region of a first conductivity type, a well region extending above the drift region and having a second conductivity type opposite the first conductivity type, an active trench extending through the well region and into the drift region, source regions having the first conductivity type formed in the well region adjacent the active trench, and a first termination trench extending below the well region and disposed at an outer edge of an active region of the device. The sidewalls and bottom of the active trench are lined with dielectric material, and substantially filled with a first conductive layer forming an upper electrode and a second conductive layer forming a lower electrode, the upper electrode being disposed above the lower electrode and separated therefrom by inter-electrode dielectric material.Type: ApplicationFiled: February 15, 2008Publication date: June 12, 2008Inventors: Ashok Challa, Alan Elbanhawy, Thomas E. Grebs, Nathan L. Kraft, Dean E. Probst, Rodney S. Ridlay, Steven P. Sapp, Qi Wang, Chongman Yun, J.G. Lee, Peter H. Wilson, Joseph A. Yedinak, J.Y. Jung, H.C. Jang, Babak S. Sanl, Richard Stokes, Gary M. Dolny, John Mytych, Becky Losee, Adam Selsley, Robert Herrick, James J. Murphy, Gordon K. Madson, Bruce D. Marchant, Christopher L. Rexer, Christopher B. Kocon, Debra S. Woolsey
-
Patent number: 7345342Abstract: Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented.Type: GrantFiled: December 29, 2004Date of Patent: March 18, 2008Assignee: Fairchild Semiconductor CorporationInventors: Ashok Challa, Alan Elbanhawy, Steven P. Sapp, Peter H. Wilson, Babak S. Sani, Christopher B. Kocon
-
Publication number: 20080007236Abstract: According to an embodiment, a power converter system includes an output node at which an output voltage is provided. A segmented power module, coupled to the output node, has a plurality of segments. Each segment is implemented with a switch having a size which is different from the size of switch used to implement any other segment.Type: ApplicationFiled: July 6, 2006Publication date: January 10, 2008Inventor: Alan Elbanhawy
-
Publication number: 20080001279Abstract: A chip module is disclosed. It includes a circuit substrate, a semiconductor die comprising a power transistor mounted on the circuit substrate, and a passive electronic component. The passive electronic component is in electrical communication with the semiconductor die, and is in thermal communication with the semiconductor die.Type: ApplicationFiled: June 30, 2006Publication date: January 3, 2008Inventors: Alan Elbanhawy, Benny Tjia
-
Publication number: 20070164428Abstract: A semiconductor assembly is disclosed. The semiconductor assembly includes a multilayer substrate having at least two layers with conductive patterns insulated by at least two dielectric layers. The substrate includes a first surface and a second surface. A leadless package comprising a control chip is coupled to the multilayer substrate. A semiconductor die comprising a vertical transistor is coupled to the multilayer substrate. There are conductive structures on the second surface for attaching the substrate to a circuit board. The control chip and the semiconductor die are in electrical communication through the multilayer substrate.Type: ApplicationFiled: January 18, 2006Publication date: July 19, 2007Inventors: Alan Elbanhawy, Benny Tjia
-
Publication number: 20070152729Abstract: A method of driving a dual-gated MOSFET having a Miller capacitance between the MOSFET gate and drain includes preparing the MOSFET to switch from a blocking mode to a conduction mode by applying to the MOSFET shielding gate a first voltage signal having a first voltage level. The first voltage level is selected to charge the Miller capacitance and thereby reduce switching losses. A second voltage signal is applied to the switching gate to switch the MOSFET from the blocking to the conduction mode. The first voltage signal is then changed to a level selected to reduce the conduction mode drain-to-source resistance and thereby reduce conduction losses. The first voltage signal is returned to the first voltage level to prepare the MOSFET for being switched from the conduction mode to the blocking mode.Type: ApplicationFiled: March 6, 2007Publication date: July 5, 2007Applicant: Fairchild Semiconductor CorporationInventor: Alan Elbanhawy
-
Patent number: 7199435Abstract: Semiconductor devices containing a MOSFET and an on-chip current sensor in the form of a magnetic resistive element are described. The magnetic resistive element (MRE) is proximate the MOSFET in the semiconductor device. The current flowing through the MOSFET generates a magnetic field that is detected by the MRE. The MRE comprises a metal film that is placed proximate the MOSFET during the normal fabrication processes, thereby adding little to the manufacturing complexity or cost. Using the MRE adds an accurate, effective, and cheap method to measure currents in MOSFET devices.Type: GrantFiled: October 9, 2003Date of Patent: April 3, 2007Assignee: Fairchild Semiconductor CorporationInventor: Alan Elbanhawy
-
Patent number: 7195979Abstract: A method of driving a dual-gated MOSFET having a Miller capacitance between the MOSFET gate and drain includes preparing the MOSFET to switch from a blocking mode to a conduction mode by applying to the MOSFET shielding gate a first voltage signal having a first voltage level. The first voltage level is selected to charge the Miller capacitance and thereby reduce switching losses. A second voltage signal is applied to the switching gate to switch the MOSFET from the blocking to the conduction mode. The first voltage signal is then changed to a level selected to reduce the conduction mode drain-to-source resistance and thereby reduce conduction losses. The first voltage signal is returned to the first voltage level to prepare the MOSFET for being switched from the conduction mode to the blocking mode.Type: GrantFiled: February 7, 2005Date of Patent: March 27, 2007Assignee: Fairchild Semiconductor CorporationInventor: Alan Elbanhawy
-
Publication number: 20060214222Abstract: Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented.Type: ApplicationFiled: May 31, 2006Publication date: September 28, 2006Inventors: Ashok Challa, Alan Elbanhawy, Thomas Grebs, Nathan Kraft, Dean Probst, Rodney Ridley, Steven Sapp, Qi Wang, Chongman Yun, J. Lee, Peter Wilson, Joseph Yedinak, J. Jung, H. Jang, Babak Sani, Richard Stokes, Gary Dolny, John Mytych, Becky Losee, Adam Selsley, Robert Herrick, James Murphy, Gordon Madson, Bruce Marchant, Christopher Rexer, Christopher Kocon, Debra Woolsey