Patents by Inventor Alan F. Hendrickson
Alan F. Hendrickson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9036091Abstract: An integrated circuit includes a tuner, a digital television (DTV) demodulator, an analog television (ATV) demodulator, and a controller. The tuner includes an input for receiving a radio frequency (RF) signal including at least one of an analog television signal and digital television signal, and including a first output terminal and a second output terminal. The DTV demodulator includes a DTV input coupled to the first output terminal of the tuner and includes a DTV output terminal. The ATV demodulator includes an ATV input coupled to the second output terminal of the tuner and includes an ATV output terminal. The controller is coupled to the tuner, the DTV demodulator, and the ATV demodulator to configure the tuner and at least one of the DTV demodulator and the ATV demodulator for receiving television content in a selected television format.Type: GrantFiled: January 6, 2011Date of Patent: May 19, 2015Assignee: Silicon Laboratories Inc.Inventors: Alan F. Hendrickson, Alessandro Piovaccari, Ramin Khoini-Poorfard, Mitchell Reid, Frederick Alan Rush, Jean-Marc Guyot, David Le Goff, Michael Robert May, Henry William Singor, Qi Cai, Peter Jozef Vancorenland, Chunyu Xin, Pascal Blouin
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Patent number: 8848110Abstract: A receiver circuit includes an analog front-end and a digital processing unit. The analog front-end includes an input for receiving a radio frequency (RF) signal, a first control input for receiving a gain adjustment signal, a second control input for receiving a timing signal, and a signal output for providing a digital intermediate frequency (IF) signal. The analog front-end updates gains of a plurality of gain stages according to the gain adjustment signal and in synchronism with the timing signal. The digital processing unit is configured to produce at least one output signal derived from the digital IF signal. The digital processing unit includes a timing recovery circuit configured to generate the timing signal based on the digital IF signal to control timing of the updating gains of each of the plurality of adjustable gain stages.Type: GrantFiled: May 28, 2010Date of Patent: September 30, 2014Assignee: Silicon Laboratories Inc.Inventors: Ramin Khoini-Poorfard, Alan F. Hendrickson, Alessandro Piovaccari, David S. Trager, Aslamali A. Rafi, Abdulkerim L. Coban, David Le Goff
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Publication number: 20120176550Abstract: An integrated circuit includes a tuner, a digital television (DTV) demodulator, an analog television (ATV) demodulator, and a controller. The tuner includes an input for receiving a radio frequency (RF) signal including at least one of an analog television signal and digital television signal, and including a first output terminal and a second output terminal. The DTV demodulator includes a DTV input coupled to the first output terminal of the tuner and includes a DTV output terminal. The ATV demodulator includes an ATV input coupled to the second output terminal of the tuner and includes an ATV output terminal. The controller is coupled to the tuner, the DTV demodulator, and the ATV demodulator to configure the tuner and at least one of the DTV demodulator and the ATV demodulator for receiving television content in a selected television format.Type: ApplicationFiled: January 6, 2011Publication date: July 12, 2012Inventors: Alan F. Hendrickson, Alessandro Piovaccari, Ramin Khoini-Poorfard, Mitchell Reid, Frederick Alan Rush, Jean-Marc Guyot, David Le Goff, Michael Robert May, Henry William Singor, Qi Cai, Peter Jozef Vancorenland, Chunyu Xin, Pascal Blouin
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Publication number: 20110235758Abstract: A receiver circuit includes an analog front-end and a digital processing unit. The analog front-end includes an input for receiving a radio frequency (RF) signal, a first control input for receiving a gain adjustment signal, a second control input for receiving a timing signal, and a signal output for providing a digital intermediate frequency (IF) signal. The analog front-end updates gains of a plurality of gain stages according to the gain adjustment signal and in synchronism with the timing signal. The digital processing unit is configured to produce at least one output signal derived from the digital IF signal. The digital processing unit includes a timing recovery circuit configured to generate the timing signal based on the digital IF signal to control timing of the updating gains of each of the plurality of adjustable gain stages.Type: ApplicationFiled: May 28, 2010Publication date: September 29, 2011Applicant: SILICON LABORATORIES, INC.Inventors: Ramin Khoini-Poorfard, Alan F. Hendrickson, Alessandro Piovaccari, David S. Trager, Aslamali A. Rafi, Abdulkerim L. Coban, David Le Goff
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Patent number: 7958286Abstract: Programmable on-chip identification circuitry and associated method are disclosed that provide integrated circuits with the ability to select and report from multiple different vendor and system identification configurations. The integrated circuit device includes programmable circuitry that utilizes vendor identification, system identification, configuration or other device information provided or selected at least in part based upon selection information from a source external to the integrated circuit. The selection information may be provided through one or more externally generated digital and/or analog control signals that are then processed within the integrated circuit device to select, access and utilize desired identification information stored in an on-chip database.Type: GrantFiled: January 19, 2006Date of Patent: June 7, 2011Assignee: Silicon Laboratories Inc.Inventors: David P. Bresemann, Alan F. Hendrickson, Robert C. Wagner
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Patent number: 7925005Abstract: A method of calibrating longitudinal balance for a subscriber line interface circuit includes providing a first and a second driver of a differential driver pair for driving a subscriber line. An output of each of the first and second drivers is coupled to a common output. The common output is coupled to an input of the first driver. The gain of at least one of the first and second drivers is adjusted until a calibration signal (V1) present at the input of the first driver is substantially the same as a calibration signal (V2) present at the input of the second driver.Type: GrantFiled: October 23, 2006Date of Patent: April 12, 2011Assignee: Silicon Laboratories, Inc.Inventors: Michael J. Mills, Marius Goldenberg, Alan F. Hendrickson, Ion C. Tesu, Jiangtao Yi
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Patent number: 7577413Abstract: According to a disclosed method, a calibration signal is provided at a first frequency corresponding to a low frequency edge of a desired passband to an input of a filter (240). A first value is measured at an output of the filter (240). The calibration signal is provided at a second frequency corresponding to a high frequency edge of the desired passband to the input of the filter (240). A second value is measured at the output of the filter (240). The first value is compared to the second value. A characteristic of the filter (240) is changed in response to the comparing. In one form, the filter is an IF filter (240) and a receiver (200) includes both the IF filter (240) and a calibration circuit (250) for forming the calibration signal and providing the calibration signal to the IF filter to change the characteristic in response to a calibration operation.Type: GrantFiled: September 19, 2006Date of Patent: August 18, 2009Assignee: Silicon Laboratories, Inc.Inventors: Chengming He, Richard A. Johnson, Alan F. Hendrickson
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Publication number: 20080111584Abstract: A method of calibrating longitudinal balance for a subscriber line interface circuit includes providing a first and a second driver of a differential driver pair for driving a subscriber line. An output of each of the first and second drivers is coupled to a common output. The common output is coupled to an input of the first driver. The gain of at least one of the first and second drivers is adjusted until a calibration signal (V1) present at the input of the first driver is substantially the same as a calibration signal (V2) present at the input of the second driver.Type: ApplicationFiled: October 23, 2006Publication date: May 15, 2008Inventors: Michael J. Mills, Marius Goldenberg, Alan F. Hendrickson, Ion C. Tesu, Jiangtao Yi
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Publication number: 20080070539Abstract: According to a disclosed method, a calibration signal is provided at a first frequency corresponding to a low frequency edge of a desired passband to an input of a filter (240). A first value is measured at an output of the filter (240). The calibration signal is provided at a second frequency corresponding to a high frequency edge of the desired passband to the input of the filter (240). A second value is measured at the output of the filter (240). The first value is compared to the second value. A characteristic of the filter (240) is changed in response to the comparing. In one form, the filter is an IF filter (240) and a receiver (200) includes both the IF filter (240) and a calibration circuit (250) for forming the calibration signal and providing the calibration signal to the IF filter to change the characteristic in response to a calibration operation.Type: ApplicationFiled: September 19, 2006Publication date: March 20, 2008Applicant: SILICON LABORATORIES, INC.Inventors: Chengming He, Richard A. Johnson, Alan F. Hendrickson
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Patent number: 7024539Abstract: Programmable on-chip identification circuitry and associated method are disclosed that provide integrated circuits with the ability to select and report from multiple different vendor and system identification configurations. The integrated circuit device includes programmable circuitry that utilizes vendor identification, system identification, configuration or other device information provided or selected at least in part based upon selection information from a source external to the integrated circuit. The selection information may be provided through one or more externally generated digital and/or analog control signals that are then processed within the integrated circuit device to select, access and utilize desired identification information stored in an on-chip database.Type: GrantFiled: July 3, 2002Date of Patent: April 4, 2006Assignee: Silicon Laboratories Inc.Inventors: David P. Bresemann, Alan F. Hendrickson, Robert C. Wagner
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Patent number: 6748515Abstract: An integrated circuit device and associated method are disclosed utilizing on-chip programmable circuitry that receives and stores vendor identification information, in particular, for devices meeting operational requirements of the Audio CODEC '97 Component Specification. The programmable circuitry allows for vendor ID information for multiple device configurations and/or multiple vendor supplied devices to be accurately reported to external devices. In particular, direct-access-arrangement (DAA) circuitry is disclosed having such on-chip programmable circuitry that may be loaded with vendor identification information at least in part from an external source. The external source may in turn be programmable circuitry, such as a EEPROM.Type: GrantFiled: July 17, 2000Date of Patent: June 8, 2004Assignee: Silicon Laboratories Inc.Inventors: Alan F. Hendrickson, Robert C. Wagner
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Publication number: 20030063726Abstract: Caller ID (CID) data-reporting circuitry operates in conjunction with direct-access arrangement (DAA) circuitry or other circuitry that operates within the operational requirements of the Audio Codec '97 (AC-97) Component Specification. The CID data-reporting circuitry provides for the transfer of a data word from the DAA circuitry to a host computer or controller that operates within the AC-97 operational specifications. The CID data-reporting circuitry transfers the CID data in an asynchronous manner, i.e., at non-pre-determined intervals. Software running on the host computer or the controller may thus examine each data word or group of data words and take appropriate action, for example, process the data further or terminate the data transfer. A command interpreter begins the data transfer by initializing an address pointer used to facilitate retrieving the data from a CID random-access memory (RAM) and to make the data available to the host computer or controller through an output register.Type: ApplicationFiled: November 25, 2002Publication date: April 3, 2003Applicant: Silicon Laboratories, Inc.Inventor: Alan F. Hendrickson
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Patent number: 6510215Abstract: Caller ID (CID) data-reporting circuitry operates in conjunction with direct-access arrangement (DAA) circuitry or other circuitry that operates within the operational requirements of the Audio Codec '97 (AC-97) Component Specification. The CID data-reporting circuitry provides for the transfer of a data word from the DAA circuitry to a host computer or controller that operates within the AC-97 operational specifications. The CID data-reporting circuitry transfers the CID data in an asynchronous manner, i.e., at non-pre-determined intervals. Software running on the host computer or the controller may thus examine each data word or group of data words and take appropriate action, for example, process the data further or terminate the data transfer. A command interpreter begins the data transfer by initializing an address pointer used to facilitate retrieving the data from a CID random-access memory (RAM) and to make the data available to the host computer or controller through an output register.Type: GrantFiled: July 17, 2000Date of Patent: January 21, 2003Assignee: Silicon Laboratories Inc.Inventor: Alan F. Hendrickson
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Publication number: 20030005274Abstract: Programmable on-chip identification circuitry and associated method are disclosed that provide integrated circuits with the ability to select and report from multiple different vendor and system identification configurations. The integrated circuit device includes programmable circuitry that utilizes vendor identification, system identification, configuration or other device information provided or selected at least in part based upon selection information from a source external to the integrated circuit. The selection information may be provided through one or more externally generated digital and/or analog control signals that are then processed within the integrated circuit device to select, access and utilize desired identification information stored in an on-chip database.Type: ApplicationFiled: July 3, 2002Publication date: January 2, 2003Inventors: David P. Bresemann, Alan F. Hendrickson, Robert C. Wagner
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Patent number: 6275519Abstract: In a digital communication receiver, a system and method for recovering the timing of frames in the received signal. The receiver synchronizes an internal frame clock with a series of received data frames in the received data stream. One embodiment of a method for performing the frame synchronization proceeds by first recovering a symbol timing for data symbols in the received frames, then acquiring a frame timing by scanning the received data symbols for the SYNC field only during a narrow detection window around an expected location in time for the SYNC field, and then locking the frame timing. An embodiment of a system for performing the frame synchronization comprises an input for receiving the data frames in the received data stream, a symbol clock that indicates symbol transitions in the received data stream, timing logic that indicates the detection window during which the a SYNC field is expected, a SYNC-field detector, and a receiver frame clock.Type: GrantFiled: September 4, 1998Date of Patent: August 14, 2001Assignee: DSP Group, Inc.Inventor: Alan F. Hendrickson
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Patent number: 6263013Abstract: In a direct sequence spread spectrum communication receiver, a system and method for recovering the timing of a pseudo-random noise (PN) sequence used for despreading the received signals. In one embodiment of the method, the receiver waits for detection of a SYNC field to confirm at least a coarse synchronization or the receiver's local PN sequence with the received PN sequence (in the received signal). The receiver then performs a fast tracking to finely synchronize the receiver's PN sequence with the received PN sequence, preferably for a fixed duration of time. One embodiment of a system for performing the synchronization with the fast tracking includes an input for receiving a received spread-spectrum data stream, an ML detection logic, a receiver PN clock, a despreading mixer that generates a narrowband signal from the spread-spectrum data stream, a testing logic that generates a PASS output if it identifies a SYNC field in the narrowband signal, and a fast-tracking logic.Type: GrantFiled: September 4, 1998Date of Patent: July 17, 2001Assignee: DSP Group, Inc.Inventor: Alan F. Hendrickson
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Patent number: 6256337Abstract: In a direct sequence spread spectrum communication system, a system and method for recovering the timing of a pseudo-random noise (PN) sequence used for despreading the received signals. In one embodiment, the communication system is a time-division duplexing (TDD) or a time-division multiple-access (TDMA) system. A receiver in the communication system uses a “sliding correlator” maximal-likelihood (ML) detection system to scan through a range of possible PN phases to determine the correct one. In one embodiment of a method for performing the synchronization, a receiver acquires the PN phase by repeating the ML detection for a time greater than or equal to the period of the TDD or TDMA frames, with a sufficiently high repetition rate to ensure that the correct PN phase is examined at least once during a received frame. The acquisition is thereby completed within a fixed amount of time.Type: GrantFiled: September 4, 1998Date of Patent: July 3, 2001Assignee: DSP Group, Inc.Inventors: Alan F. Hendrickson, Ken M. Tallo
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Patent number: 6256335Abstract: In a direct sequence spread spectrum communication receiver, a system and method for recovering the timing of a pseudo-random noise (PN) sequence used for despreading the received signals. In one embodiment, the receiver performs a slow tracking to maintain the synchronization of the receiver's PN sequence with the received PN sequence. The slow tracking preferably includes one or more advancements or delays of the receiver's PN sequence if correlation measurements consistently indicate that the receiver's PN sequence lags or leads the received PN sequence. The slow tracking preferably also includes a long-term adjustment of the receiver's PN phase, distributed over a number of received frames, to compensate for any frequency offsets between the receiver's PN sequence and the received PN sequence.Type: GrantFiled: September 4, 1998Date of Patent: July 3, 2001Assignee: DSP Group, Inc.Inventor: Alan F. Hendrickson
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Patent number: 6212246Abstract: In a digital communications receiver, a system and method for evaluating the quality of received symbols and for initializing and adjusting a symbol clock. The invention presents a symbol quality detector that evaluates symbols which have been received by the receiver and detected in a matched filter. The received symbols are members of a constellation with elements that have purely I or purely Q components. The symbol-quality detector comprises inputs that receive the I and Q components of the symbols, and a logic block that generates the symbol-quality signal by constructing the quantity ||I|−|Q||. This quantity is a maximum when the detected symbols are aligned with the expected points in the symbol constellation, and decreases if the detected symbols are rotated away from these constellation points. The present invention further comprises a digital communications receiver that uses a symbol-quality detector to evaluate its symbol clock.Type: GrantFiled: May 13, 1998Date of Patent: April 3, 2001Assignee: DSP Group, Inc.Inventor: Alan F. Hendrickson
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Patent number: 6097768Abstract: A phase detector using simple arithmetic operations to measure phase errors in the carrier-recovery mechanism for a DQPSK digital communications receiver. The carrier-recovery mechanism is a feedback loop that provides a synchronization between the oscillators in the transmitter and receiver of the communications system; the phase detector measures deviations from this synchronization and generates a phase-error signal used in the feedback loop to synchronize the oscillators. To perform this measurement, the phase detector takes the received signal as input and compares it against a local oscillator in the receiver to generate two digital signals: the in-phase (I) and quadrature-phase (Q) components of the received signal. These signals are the input to a logic unit, which uses these two signals to determine the phase-error signal.Type: GrantFiled: November 12, 1997Date of Patent: August 1, 2000Assignee: DPS Group, Inc.Inventors: Stephen T. Janesch, Alan F. Hendrickson, Paul G. Schnizlein