Abstract: A method of operating a vehicle climate system when an ambient temperature is below a threshold temperature is provided. In response to an ambient temperature being less than a threshold temperature, a controller is adapted to operate a blower motor at a voltage that depends on whether the vehicle is in charge sustain mode or charge deplete mode. In response to an ambient temperature being greater than a threshold temperature, the controller is adapted to operate the blower motor at a voltage that does not depend on whether in the charge sustain or charge deplete modes.

Abstract: A benchmarking mechanism numerically analyzing stalls in a pipelined CPU. Each stage in the CPU is instrumented with dedicated stall counters. For each clock cycle and for each CPU stage, the technology described herein determines whether the stage is stalled, counts the number of stalls per stage, determines why the stage is stalled, and determines which instruction is in the stalled processor stage along with its program address.

Abstract: A file archive system for storing multiple files and directories as a single file. The file archive system could be used on a hand-held computer or other computing device. The file archive system in a preferred embodiment has an operating system with a loadable file system. In another embodiment, the file archive system includes a file archive structure for storing multiple files as a single file.

Abstract: A simulation of an electronics system which performs a set of operations of interest. A simulated supervisory circuit detects a state in which all the operations have been completed, and also determines the amount of time until the occurrence of the next relevant event. Simulation time is then advanced by that amount of time. This enables simulation time corresponding to an inactive system to be eliminated.

Abstract: An integrated circuit with a multiplexer system and a control circuit is described. The multiplexer system has an output terminal connected to an output pin of the integrated circuit and input terminals connected to internal nodes of the integrated circuit. In a normal mode the control circuit generates the control signals so that any one of the internal nodes is connected to the output pin so that the integrated circuit can function flexibly. In a test mode so that a different internal node is connected to the output pin in each cycle of a test clock signal.

Abstract: An embodiment of the present invention may provide a software tool adapted to run on a handheld computer for providing a mock-up graphical user interface on a display screen of the handheld computer for use in demonstrating the look and feel of a proposed software product. A demonstration file adapted to be executed on a handheld computer device may include sets of screen instructions for providing at least two of the screen displays. At least one of the sets of screen instructions includes a screen name, a jump reference, and at least one text anchor element and/or at least one image anchor element. A text anchor element and/or an image anchor element uses an absolute screen position specification providing an absolute pixel location for specifying a location on the screen for placement of text and/or an image. Preferably the demonstration file is formatted as a well-formed XML document.

Abstract: A compact menu structure for computing devices with a small display screen. The menu structure reduces the number of menu panels displayed on the screen while still providing the user with a visible representation of the menu structure. In an embodiment of the present invention, an application program on a handheld calculator or other small screen computer device provides a compact menu structure that has a navigation bar and a single submenu panel. The navigation bar displays the menu tree for the menu displayed in the submenu panel. The navigation bar may wrap to multiple line for deep menu structures. Other embodiments include a sliding bar in the menu sub-panel for sub-panels that have more items than will fit in the sub-panel.

Abstract: A file archive system for storing multiple files and directories as a single file. The file archive system could be used on a hand-held computer or other computing device. The file archive system in a preferred embodiment has an operating system with a loadable file system. In another embodiment, the file archive system includes a file archive structure for storing multiple files as a single file.

Abstract: A filter press having a horizontal stack of filter plate assemblies, in which removal of filter cake is automated by means of a vibration/shifter carriage that can be moved in steps along a stack of filter plates after a press closing head has been retracted. At each step, the carriage opens up a group of filter plates. The plates are vibrated vertically by cams carried by the carriage. The vibrating action alternately tensions and relaxes the filter cloth for dislodging accumulated filter cake. An improved cylinder and ram arrangement for actuating the closing head is also disclosed and comprises oppositely acting cylinder and ram units carried by an intermediate travelling cylinder carriage. The arrangement achieves the advantages of a telescopic cylinder and ram unit, but at lower cost.

Abstract: A computer system simulator concurrently models both processor operation and signal logic behavior and provides a high degree of user interaction and flexibility in the observation and control of signal values and memory contents during the execution of a simulation. During simulation, source equations for signals can be requested for display either through direct input of a signal name or through graphical interface with the simulation display. Signal equations can in this manner be traced back through several levels, which conveniently provides important information during the observation and modification of signal values. Memory areas may be associated with a processor and loaded with data to be executed by that processor during the simulation. The data can be displayed in both numerical and assembly code mnemonic form, and may also be modified by entering numbers or assembly instructions. The simulated processor execution may thus be interactively modified during the simulation.

Abstract: The present invention provides for a computer system having a plurality of parallel processor units with each processor unit associated with at least one register for receiving data for the processor unit. The computer system has a bus unit, coupled to the output of each processor unit and the associated register of each processor unit, to transfer the output data of a first processor unit into an associated register of a second processor unit in a single computer operation. The second processor unit is prevented from reading the associated register until the bus unit transfers the output data from the first processor unit to the second processor unit.

Abstract: A technique for speeding CPU operations in handling branch instructions in which the target instructions is a short displacement away from its branch instruction is disclosed. When the target instruction is displaced within a predetermined number of instructions away, a logic block and counter issue an invalidating control signal which invalidates the execution of the branch instruction and instructions between the branch instruction and the target instruction. The invalidating control signal is removed when the target instruction is reached. Time is saved if the latency of the computer system is longer than the time required to cycle the instruction queue to the target instruction.

Abstract: The present invention provides for a computer system having a plurality of parallel processor units. The processor units are connected in common to a signal line with each processor capable of setting a first signal level on the line and monitoring the line in response to instructions to the processor. This allows each processor unit to be notified of the completion of a parallel operation by other participating processor units upon a second signal level on the signal line. More than one signal lines may be connected between the parallel processor units to provide synchronization of different parallel operations between different processor units.

Abstract: A parallel processing system is provided with a plurality of processors and a plurality of memories, and bus units with arbitration coupling the processors and memories. A bus unit provides a pathway between one processor and the bus unit's respective memory. Each bus unit arbitrates multiple simultaneous access requests for its respective memory and communicates its decisions to other bus units so that a memory access requiring multiple memories will only occur if all those memories are available. The coupling of processors to memories can change, dynamically, each bus cycle without the need for setup before the bus cycle either by pipelining or having unused bus cycles. In a specific embodiment, the memory access information is provided on high order address lines, where the processor logically accesses different memory address spaces to make different accesses, thereby sharing memory with other processors.

Abstract: A computer system having a plurality of parallel processor units with each processor unit having an output bus of n bits and an associated mask register is provided. The computer system comprises a bus unit, coupled to the output bus of each processor unit and each associated mask register, for masking the output bus bits with bits in the mask register of each processor unit and logically combining the resulting masked bits from each processor unit into an output bus of n bits in one computer operation.

Abstract: A computer system simulator concurrently models both processor operation and signal logic behavior and provides a high degree of user interaction and flexibility in the observation and control of signal values and memory contents during the execution of a simulation. During simulation, source equations for signals can be requested for display either through direct input of a signal name or through graphical interface with the simulation display. Signal equations can in this manner be traced back through several levels, which conveniently provides important information during the observation and modification of signal values. Memory areas may be associated with a processor and loaded with data to be executed by that processor during the simulation. The data can be displayed in both numerical and assembly code mnemonic form, and may also be modified by entering numbers or assembly instructions. The simulated processor execution may thus be interactively modified during the simulation.

Abstract: A computer system having a plurality of parallel processor units with each processor unit having an output bus of n bits and an associated mask register is provided. The computer system comprises a bus unit, coupled to the output bus of each processor unit and each associated mask register, for masking the output bus bits with bits in the mask register of each processor unit and logically combining the resulting masked bits from each processor unit into an output bus of n bits in one computer operation.