Abstract: A computing system with connecting boards may include a first compute board, a second compute board, and a first connecting board connected to the first compute board and to the second compute board. The first compute board and the second compute board may include a plurality of compute elements. The first compute board, the second compute board, and the first connecting board may include a first plurality of switches including a first switch connected to a first compute element of the plurality of compute elements and a second switch connected to a second compute element of the plurality of compute elements. The first connecting board may include a first conductor, the first conductor being a conductor of a first data connection between the first switch and the second switch.

Abstract: A device and method that implements a multi-stage electrical interconnection network is provided. The electronic device includes a plurality of computing devices and a plurality of switches grouped into a plurality of groups. Switches, of the plurality of switches, in a same group are configured to be fully connected to computing devices in the same group, each of switches of the plurality of switches included in a first group among the plurality of groups is configured to have a ono-to-one connection with any one of switches included in a second group, and a connection between the computing devices in the same group and the switches in the same group and a connection between switches in in the plurality of groups are electrical connections.

Abstract: A device and method that implements a multi-stage electrical interconnection network is provided. The electronic device includes a plurality of computing devices and a plurality of switches grouped into a plurality of groups. Switches, of the plurality of switches, in a same group are configured to be fully connected to computing devices in the same group, each of switches of the plurality of switches included in a first group among the plurality of groups is configured to have a ono-to-one connection with any one of switches included in a second group, and a connection between the computing devices in the same group and the switches in the same group and a connection between switches in in the plurality of groups are electrical connections.

Abstract: A system and method for cache management. In some embodiments, a system includes: a lower-level cache; a first upper-level cache; and a second upper-level cache, the lower-level cache, the first upper-level cache, and the second upper-level cache being configured: to store first metadata of a cache line, in the first upper-level cache, the first metadata indicating that the cache line is in a partial state, the partial state indicating that at least two words in the cache line are in different permission states.

Abstract: Systems and methods for computing with multiple nodes. In some embodiments, a method includes: executing, by a first node of a plurality of nodes, a global load from a first address of a shared memory, the shared memory being shared by the nodes, the first address being an address within a shared memory section of a second node, the first address being cached in a first cache of the first node, the executing including: fetching a value stored in the shared memory, at the first address.

Abstract: Systems and methods for computing with multiple nodes. In some embodiments, a method includes writing, during each of a sequence of time steps, by each node of a plurality of nodes, to a shared memory, the shared memory being shared by the nodes, wherein: each of the nodes includes a hardware-maintained coherence domain and is connected to the other nodes, and each of the nodes includes a respective portion of the shared memory.

Abstract: Systems and methods for computing with multiple nodes. In some embodiments, a method includes: executing, by a first node of a plurality of nodes, a global clean, the executing including: determining that a first cached value in a cache of the first node is a modified cached copy of data in a shared memory, the shared memory being shared by the nodes; and in response to determining that the first cached value is a modified cached copy of data in the shared memory, writing back the first cached value to the shared memory.

Abstract: Message splitting and aggregation in a multi-stage electrical interconnection network are disclosed. A method of operating an electronic device comprised of computing devices, includes splitting, into segments, a message to be transmitted from a first of the computing devices, transmitting the segments to a second of the computing devices through a multi-channel that is based on an electrical connection between the first computing device and a plurality of switches, wherein the multi-channel includes channels respectively including electrical connections, the electrical connections connecting the first computing device with the second computing device, and reconstructing the message by aggregating the segments in the second computing device, wherein a bandwidth of the multi-channel transmitting the segments is greater than a maximum bandwidth of a single electrical connection of the electrical connections.

Abstract: A system and method for address translation in a multi-node computing system. In some embodiments, the system includes a first node. The first node may include: a core; and a global address translation circuit, the core including: a core processing circuit; and a memory management unit configured to map local virtual addresses to global virtual addresses, the global address translation circuit being configured to map global virtual addresses to global physical addresses.

Abstract: Embodiments disclose methods, systems and devices including a plurality of connectors, a plurality of switches, and a plurality of compute elements. Each of the plurality of compute elements may be connected to each of the plurality of switches. In some embodiments, a first subset of the plurality of switches may be directly connected to a first subset of the plurality of the connectors in a fanout mechanism, and a second subset of the plurality of switches may be directly connected to a second subset of the plurality of the connectors in a similar fanout mechanism.

Abstract: Systems and methods for computing with multiple nodes. In some embodiments, the method includes: determining that a first data value in a cache is a global data value; setting a first flag to indicate that the first data value is a global data value; and selectively invalidating one or more portions of the cache, wherein the selective invalidating of the cache includes: determining, based on the first flag, that the first data value is a global data value; and based on the determining, invalidating the first data value.

Abstract: Systems and methods for computing with multiple nodes. In some embodiments, a method includes: reading, by a first node of a plurality of nodes, from a shared memory shared by the nodes, a first data value; modifying, by the first node, the first data value; storing, by the first node, the modified first data value in a cache of the first node; initiating, by the first node, a global synchronization command; and in response to the initiating, by the first node, of the global synchronization command: indicating, by the first node, that the first node has completed a time step synchronization.

Abstract: A computing system with connecting boards. In some embodiments, the computing system includes a first compute board, a second compute board, and a first connecting board connected to the first compute board and to the second compute board. The first compute board and the second compute board may include a plurality of compute elements. The first compute board, the second compute board, and the first connecting board may include a first plurality of switches including a first switch connected to a first compute element of the plurality of compute elements and a second switch connected to a second compute element of the plurality of compute elements. The first connecting board may include a first conductor, the first conductor being a conductor of a first data connection between the first switch and the second switch.

Abstract: A device and method that implements a multi-stage electrical interconnection network is provided. The electronic device includes a plurality of computing devices and a plurality of switches grouped into a plurality of groups. Switches, of the plurality of switches, in a same group are configured to be fully connected to computing devices in the same group, each of switches of the plurality of switches included in a first group among the plurality of groups is configured to have a ono-to-one connection with any one of switches included in a second group, and a connection between the computing devices in the same group and the switches in the same group and a connection between switches in in the plurality of groups are electrical connections.

Abstract: A computing device includes: a processor; a memory stack in which memories connected to the processor are stacked; and a substrate disposed under the processor, wherein a network bandwidth between the processor and the substrate is five or less times a memory bandwidth between the processor and the memory stack.

Abstract: Message splitting and aggregation in a multi-stage electrical interconnection network are disclosed. A method of operating an electronic device comprised of computing devices, includes splitting, into segments, a message to be transmitted from a first of the computing devices, transmitting the segments to a second of the computing devices through a multi-channel that is based on an electrical connection between the first computing device and a plurality of switches, wherein the multi-channel includes channels respectively including electrical connections, the electrical connections connecting the first computing device with the second computing device, and reconstructing the message by aggregating the segments in the second computing device, wherein a bandwidth of the multi-channel transmitting the segments is greater than a maximum bandwidth of a single electrical connection of the electrical connections.

Abstract: A device and method that implements a multi-stage electrical interconnection network is provided. The electronic device includes a plurality of computing devices and a plurality of switches grouped into a plurality of groups. Switches, of the plurality of switches, in a same group are configured to be fully connected to computing devices in the same group, each of switches of the plurality of switches included in a first group among the plurality of groups is configured to have a ono-to-one connection with any one of switches included in a second group, and a connection between the computing devices in the same group and the switches in the same group and a connection between switches in in the plurality of groups are electrical connections.

Abstract: A computing device includes: a processor; a memory stack in which memories connected to the processor are stacked; and a substrate disposed under the processor, wherein a network bandwidth between the processor and the substrate is five or less times a memory bandwidth between the processor and the memory stack.

Abstract: Embodiments of the invention provide a method, system and computer program product for embedding a global barrier and global interrupt network in a parallel computer system organized as a torus network. The computer system includes a multitude of nodes. In one embodiment, the method comprises taking inputs from a set of receivers of the nodes, dividing the inputs from the receivers into a plurality of classes, combining the inputs of each of the classes to obtain a result, and sending said result to a set of senders of the nodes. Embodiments of the invention provide a method, system and computer program product for embedding a collective network in a parallel computer system organized as a torus network. In one embodiment, the method comprises adding to a torus network a central collective logic to route messages among at least a group of nodes in a tree structure.

Abstract: Methods, systems and computer program products are disclosed for measuring a performance of a program running on a processing unit of a processing system. In one embodiment, the method comprises informing a logic unit of each instruction in the program that is executed by the processing unit, assigning a weight to each instruction, assigning the instructions to a plurality of groups, and analyzing the plurality of groups to measure one or more metrics. In one embodiment, each instruction includes an operating code portion, and the assigning includes assigning the instructions to the groups based on the operating code portions of the instructions. In an embodiment, each type of instruction is assigned to a respective one of the plurality of groups. These groups may be combined into a plurality of sets of the groups.