Abstract: A measurement device for measurement of liquid contained in a tank, particularly a fuel tank on an aircraft or boat. The device has a first pressure sensor for mounting outside the tank, on a liquid outlet pipe connected to the tank to measure the pressure of liquid in the outlet pipe. A second pressure sensor measures the pressure in the ullage space above liquid in the tank. A venturi flow meter mounted in the outlet pipe measures liquid flow through the outlet pipe. The device also includes an accelerometer. The quantity of liquid in the tank can be calculated in response to measured values received from the pressure sensors, the accelerometer and the venturi.

Abstract: A method is described. The method includes enabling and configuring poll mode for a near field communication (NFC) data exchange format (NDEF) radio frequency (RF) interface configuration. The method also includes determining that a remote NFC endpoint includes an NFC forum tag once an NFC controller (NFCC) has successfully completed protocol activation. The method further includes performing activation operations based on an RF protocol of the NFC forum tag.

Abstract: Aspects disclosed herein relate to activating a single wire protocol (SWP) interface with a circuit card. A single wire protocol (SWP) activation procedure is initiated with a circuit card. During the SWP activation procedure, an unexpected frame may be received, and a different SWP activation procedure may be initiated with the circuit card based at least in part on receiving the unexpected frame during the SWP activation procedure.

Abstract: Aspects disclosed herein relate to partitioning LLCP responsibilities between the NFCC and DH. In an example, with a NFC device a DH maybe configured to establish a LLCP link with a remote NFC endpoint through a NFCC, and partition LLCP related responsibilities between the DH and the NFCC when the NFCC is operable for LLCP split communications. Further, the NFCC may be operable to receive a PDU from a remote NFC endpoint, determine whether the received PDU is a SYMM PDU or a link deactivation PDU, and communicate the received PDU to a DH upon a determination that the received PDU is not a SYMM PDU or a link deactivation PDU.

Abstract: Aspects disclosed herein relate to activating a single wire protocol (SWP) interface with a circuit card. A single wire protocol (SWP) activation procedure is initiated with a circuit card. During the SWP activation procedure, an unexpected frame may be received, and a different SWP activation procedure may be initiated with the circuit card based at least in part on receiving the unexpected frame during the SWP activation procedure.

Abstract: Aspects disclosed herein relate to improving mechanisms for managing logical connection establishment between NFCC and a DH. In one example, with a NFC device a NFCC may be configured to receive a core initialization command, from a DH, as part of an initialization and activation procedure. The NFCC may be configured to transmit a core initialization response to the DH without information associated with a static RF connection. Thereafter, the NFC device may detect one or more remote NFC endpoints. The NFCC may further be operable to determine a maximum payload size and an initial number of credits for the static RF connection based, at least in part, on at least one of a RF interface or a RF protocol used by a remote NFC endpoint chosen for communications, and transmit the determined maximum payload size and the initial number of credits to the DH to establish a logical connection.

Abstract: A method is described. The method includes enabling and configuring poll mode for a near field communication (NFC) data exchange format (NDEF) radio frequency (RF) interface configuration. The method also includes determining that a remote NFC endpoint includes an NFC forum tag once an NFC controller (NFCC) has successfully completed protocol activation. The method further includes performing activation operations based on an RF protocol of the NFC forum tag.

Abstract: A data converter can include a resistor network, a switch network connected to the resistor network and having a plurality of switch circuits, each with an NMOS and a PMOS switch transistor, and a voltage generator to generate a drive voltage for driving a gate of at least one of the NMOS or PMOS switch transistors of at least one of the switch circuits. The voltage generator can include first and second pairs of transistors, each pair having connected control terminals and being connected to a second NMOS or PMOS transistor, a first or second resistor, and the other pair of transistors. The first and second resistors can have substantially equal resistance values. A ratio of width-to-length ratios of the second NMOS to PMOS transistors can be substantially equal to such a ratio of the switch circuit NMOS to PMOS transistors.

Abstract: The present application presents example data routing methods and apparatuses for reducing the amount of nonvolatile memory required to store secure element application locations associated with a near-field communications device. For example, the present disclosure presents a method of communication routing in a near-field communication device, which can include receiving, at a near-field communications controller (NFCC), a routing request message (e.g. from a requesting device), wherein the routing request message includes an original application identifier (AID) associated with an application. The example method may also include generating a compressed AID by applying a hash function to the original AID, reading an entry corresponding to the compressed AID in a routing data structure, wherein the entry contains one or more secure element pointers associated with one or more secure elements, and querying at least one of the secure elements to determine whether each contains the application.

Abstract: A data converter can include a resistor network, a switch network connected to the resistor network and having a plurality of switch circuits, each with an NMOS and a PMOS switch transistor, and a voltage generator to generate a drive voltage for driving a gate of at least one of the NMOS or PMOS switch transistors of at least one of the switch circuits. The voltage generator can include first and second pairs of transistors, each pair having connected control terminals and being connected to a second NMOS or PMOS transistor, a first or second resistor, and the other pair of transistors. The first and second resistors can have substantially equal resistance values. A ratio of width-to-length ratios of the second NMOS to PMOS transistors can be substantially equal to such a ratio of the switch circuit NMOS to PMOS transistors.

Abstract: Aspects disclosed herein relate to improving mechanisms for managing logical connection establishment between NFCC and a DH. In one example, with a NFC device a NFCC may be configured to receive a core initialization command, from a DH, as part of an initialization and activation procedure. The NFCC may be configured to transmit a core initialization response to the DH without information associated with a static RF connection. Thereafter, the NFC device may detect one or more remote NFC endpoints. The NFCC may further be operable to determine a maximum payload size and an initial number of credits for the static RF connection based, at least in part, on at least one of a RF interface or a RF protocol used by a remote NFC endpoint chosen for communications, and transmit the determined maximum payload size and the initial number of credits to the DH to establish a logical connection.

Abstract: A device and method are provided to drive piezoelectric elements in haptic applications. In one embodiment, a pattern generator provides user programmable PWM waveforms to a driver. The load of the driver is an inductor in series with the piezoelectric element. The filtration of the inductor in series with the capacitance of the piezoelectric element suppresses the high-frequency components of the PWM pulse train, and recovers a value commensurate with the duty cycle of the PWM pulse train. The resulting waveform across the piezoelectric element is converted to physical motion, thereby creating a haptic effect on a user interface. Advantageously, there is reduced power loss, reduced switching induced noise, and a more haptic rich environment.

Abstract: A device and method are provided to drive piezoelectric elements in haptic applications. In one embodiment, a pattern generator provides user programmable PWM waveforms to a driver. The load of the driver is an inductor in series with the piezoelectric element. The filtration of the inductor in series with the capacitance of the piezoelectric element suppresses the high-frequency components of the PWM pulse train, and recovers a value commensurate with the duty cycle of the PWM pulse train. The resulting waveform across the piezoelectric element is converted to physical motion, thereby creating a haptic effect on a user interface. Advantageously, there is reduced power loss, reduced switching induced noise, and a more haptic rich environment.

Abstract: A digital to analog converter comprising: a digital to analog conversion core adapted to receive at least one reference voltage and a digital word to be converted, and to output an analog voltage as a function of the digital word and the at least one reference voltage; a sensing circuit for sensing a difference between a first ground voltage associated with an output of the digital to analog converter and a ground reference voltage occurring at the digital to analog converter; and a compensation circuit for applying a compensation voltage to the at least one reference voltage used by the conversion core of the digital to analog converter.

Abstract: A digital to analog converter comprising: a digital to analog conversion core adapted to receive at least one reference voltage and a digital word to be converted, and to output an analog voltage as a function of the digital word and the at least one reference voltage; a sensing circuit for sensing a difference between a first ground voltage associated with an output of the digital to analog converter and a ground reference voltage occurring at the digital to analog converter; and a compensation circuit for applying a compensation voltage to the at least one reference voltage used by the conversion core of the digital to analog converter.

Abstract: A feedback circuit for an operational amplifier is provided, the circuit comprising a first impedance element in a current flow path between an output of the operational amplifier and a first node, wherein a plurality of impedance elements are, in response to a control signal, selectively connectable either between the first node and a first input of the operational amplifier, or between the first node and a further node, and the further node and the first input of the operational amplifier are at the same potential such that a voltage at the first node is independent of the control signal.

Abstract: A single chip dual function 10 Base-T/100 Base-X physical layer interface device (PHY) compatible with existing 5 V parts is provided. The PHY includes a media-independent interface (MII) and connects to an unshielded twisted pair cable via an isolation transformer and a single RJ45 connector. The PHY includes built-in auto-negotiation circuitry that allows for automatic selection of half/full duplex 10 Base-T and 100 Base-TX, while auto-polarity correction circuitry ensures immunity to receive pair reversal in the 10 Base-T mode of operation. The PHY includes internal PLL circuitry that uses a single 20 MHz clock or crystal, but that is suitable for either speed mode. The PHY includes low-power and power down modes. The 10 Base-T portions of the PHY include smart squelch for improved receive noise immunity. The PHY includes high jitter tolerance clock recovery circuitry and transmit jabber detection circuitry. The 10 Base-T portions of the PHY include on board transmit waveshaping.