Abstract: A method for fabricating custom integrated circuits includes the steps of 1) patterning a photoresist layer on an insulative layer with a standard via precision mask to define all possible vias, and 2) using a targeting energy beam to select the desired via locations, which are then etched and interconnections made, for customization or repair of the integrated circuit. Consequently, the present invention requires no custom mask so that application specific integrated circuits (ASICs) can be produced with lower lead-time and costs when compared to prior methods.

Abstract: A method for fabricating custom integrated circuits includes the steps of 1) patterning the layer to be customized with standard precision masking techniques to define all possible connections, vias or cut-points, and 2) using a non-precision targeting energy beam to select the desired connections, vias or cut-points for customization. Consequently, the present invention requires no custom mask so that application specific integrated circuits (ASICs) can be produced with lower lead-time and costs when compared to prior methods.In other embodiments, a non-precision configuration mask may replace the targeting energy beam, where the configuration mask can be made by conventional mask-making techniques or by applying an opaque layer to a mask blank and using a targeting energy beam to selectively remove the desired portions of the opaque areas.

Abstract: In accordance with this invention, integrated circuits are manufactured using parallel processing to manufacture separately selected parts of finished integrated circuits. Upon completion of the parts, the parts are joined together to form the completed integrated circuit. For example, a semiconductor wafer containing active and passive semiconductor regions is fabricated through the first layer of insulation and first conductive contacts. Separately, an interconnect structure is fabricated on a separate fabrication line to include all the layers of interconnects required to form a completed integrated circuit when joined to the wafer. The interconnect structure is joined to the wafer to form the complete integrated device. The interconnect structure can be fabricated to exclude from the integrated circuit those portions of the wafer which have been determined by test to be defective.