Patents by Inventor Alan H. Woosley

Alan H. Woosley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7374971
    Abstract: An integrated circuit has a semiconductor substrate and an interconnect layer that mechanically relatively weak and susceptible to cracks and delamination. In the formation of the integrated circuit from a semiconductor wafer, a cut is made through the interconnect layer to form an edge of the interconnect layer. This cut may continue completely through the wafer thickness or stop short of doing so. In either case, after cutting through the interconnect layer, a reconditioning layer is formed on the edge of the interconnect layer. This reconditioning layer seals the existing cracks and delaminations and inhibits the further delamination or cracking of the interconnect layer. The sealing layer may be formed, for example, before the cut through the wafer, after the cut through the wafer but before any packaging, or after performing wirebonding between the interconnect layer and an integrated circuit package.
    Type: Grant
    Filed: April 20, 2005
    Date of Patent: May 20, 2008
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Yuan Yuan, Kevin J. Hess, Chu-Chung Lee, Tu-Anh Tran, Donna Woosley, legal representative, Alan H. Woosley
  • Patent number: 7105383
    Abstract: A semiconductor die is housed in a package body. Leads, which are electrically coupled to the semiconductor die, extend from the package body and are for connecting to a printed circuit board or other device. The leads are coated with a material that protects the leads from oxidation. The coating is compatible with solder techniques that are commonly used to attach packaged semiconductors to a printed circuit board. In some examples, the coating is removable, after drying, at temperatures below one hundred eighty degrees Celsius. This allows for solder processes, which are typically at least 180° C., to remove the coating thereby exposing the leads, which has been protected from oxidation, so that it can be soldered to the printed circuit board. In some examples, the coating material includes an organic material. In some examples, the coating material is an organic solderability preservative (OSP).
    Type: Grant
    Filed: August 29, 2002
    Date of Patent: September 12, 2006
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Nhat D. Vo, Alan H. Woosley
  • Patent number: 7015585
    Abstract: An integrated circuit is packaged using a package substrate that has a bottom side with a regular array of connection points and a top side with the integrated circuit on it. The package substrate also has vias that are present to provide electrical connection between the top and bottom sides. The vias have a via capture pad that is used to directly receive a wire bond. Thus, the wires from the integrated circuit to the top side directly contact the vias at their capture pads. In such a connection there is then no need for a trace from location where the wire is bonded on the top side to the via. This saves cost. Further this makes the package substrate useful for more than one type of integrated circuit.
    Type: Grant
    Filed: December 18, 2002
    Date of Patent: March 21, 2006
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Susan H. Downey, Sheila F. Chopin, Peter R. Harper, Sohrab Safai, Tu-Anh Tran, Alan H. Woosley
  • Patent number: 6998952
    Abstract: An inductive device (105) is formed above a substrate (225) having a conductive coil formed around a core (109). The coil comprises segments formed from a first plurality of bond wires (113) and a second plurality of bond wires (111). The first plurality of bond wires (113) extends between the core (109) and the substrate (225). Each of the first plurality of bond wires is coupled to two of a plurality of wire bond pads (117, 116). The second plurality of bond wires (111) extends over the core (109) and is coupled between two of the plurality of wire bond pads (117, 119). A shield (141) includes a portion that is positioned between the core (109) and the substrate (225).
    Type: Grant
    Filed: December 5, 2003
    Date of Patent: February 14, 2006
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Yaping Zhou, Susan H. Downey, Sheila F. Chopin, Tu-Anh Tran, Alan H. Woosley, Peter R. Harper, Perry H. Pelley, III
  • Publication number: 20040119168
    Abstract: An integrated circuit is packaged using a package substrate that has a bottom side with a regular array of connection points and a top side with the integrated circuit on it. The package substrate also has vias that are present to provide electrical connection between the top and bottom sides. The vias have a via capture pad that is used to directly receive a wire bond. Thus, the wires from the integrated circuit to the top side directly contact the vias at their capture pads. In such a connection there is then no need for a trace from location where the wire is bonded on the top side to the via. This saves cost. Further this makes the package substrate useful for more than one type of integrated circuit.
    Type: Application
    Filed: December 18, 2002
    Publication date: June 24, 2004
    Inventors: Susan H. Downey, Sheila F. Chopin, Peter R. Harper, Sohrab Safai, Tu-Anh Tran, Alan H. Woosley
  • Publication number: 20040041241
    Abstract: A semiconductor die is housed in a package body. Leads, which are electrically coupled to the semiconductor die, extend from the package body and are for connecting to a printed circuit board or other device. The leads are coated with a material that protects the leads from oxidation. The coating is compatible with solder techniques that are commonly used to attach packaged semiconductors to a printed circuit board. In some examples, the coating is removable, after drying, at temperatures below one hundred eighty degrees Celsius. This allows for solder processes, which are typically at least 180° C., to remove the coating thereby exposing the leads, which has been protected from oxidation, so that it can be soldered to the printed circuit board. In some examples, the coating material includes an organic material. In some examples, the coating material is an organic solderability preservative (OSP).
    Type: Application
    Filed: August 29, 2002
    Publication date: March 4, 2004
    Inventors: Nhat D. Vo, Alan H. Woosley
  • Patent number: 5708300
    Abstract: An overmolded semiconductor device (30, 50) has a contoured package body profile instead of a conventional flat package body surface for uniform filling during the molding process. A cross-section of the semiconductor device reveals a substantially uniform thickness of plastic (36 and 38) covering the carrier substrate (14) and overmolding the semiconductor die (12). Alternatively, a thicker layer of plastic (58) overmolds the semiconductor die (12') than the layer of plastic (56) covering the carrier substrate (14'). The contoured package body profile is designed to allow a uniform flow front progression of molding compound during the molding process to eliminate voids in the package body by providing the same resistive pressure to the molding compound flow front during filling.
    Type: Grant
    Filed: September 5, 1995
    Date of Patent: January 13, 1998
    Inventors: Alan H. Woosley, Everitt W. Mace
  • Patent number: 5656549
    Abstract: A method of packaging a semiconductor device includes providing a chase (11) with a cavity (12). The cavity (12) has a cavity sidewall (13). A substrate (19) is provided having a substrate sidewall (20) wherein the substrate (19) is positioned in the cavity (12). A space or gap (21) is formed between the substrate sidewall (20) and the cavity sidewall (13). To insulate the gap (21) from mold compound (27), a barrier layer (22) is placed adjacent to the chase (11) and adjacent to the substrate (19) wherein the barrier layer (22) overlays a portion of the space or gap (21). Mold compound (27) is injected over the barrier layer (22), over the portion of the space or gap (21), and toward the substrate (19). The barrier layer (22) is used to prohibit the mold compound (27) from contacting the substrate sidewall (20) and the cavity sidewall (13) when the substrate (19) is being encapsulated.
    Type: Grant
    Filed: August 19, 1996
    Date of Patent: August 12, 1997
    Assignee: Motorola, Inc.
    Inventors: Alan H. Woosley, Harold A. Downey, Jr., Everitt W. Mace
  • Patent number: 5517056
    Abstract: A leadframe (30) having a novel resin injecting area (44) is disclosed to facilitate and control the removal of a molded gate (18) prior to excising a semiconductor device(70) from a carrier ring (14). The carrier ring has a corner which is on a diagonal with a corner of the package body (12) to form the resin injecting area. The resin injecting area of the leadframe has a hole (48) and an extension bar (50) extending from the hole to connect to a tie bar (36), which supports a die pad (32), inside the package body. The hole in the leadframe is designed for retaining a molded gate. The extension bar is designed to make the removal of a portion of a molded gate easier and more controllable. The semiconductor device can be shipped in the carrier ring with a portion of the molded gate already removed.
    Type: Grant
    Filed: September 30, 1993
    Date of Patent: May 14, 1996
    Assignee: Motorola, Inc.
    Inventors: Charles G. Bigler, Alan H. Woosley, Michael B. McShane
  • Patent number: 5344600
    Abstract: A method of encapsulating a semiconductor device permits use of the same mold for various package types. In one form, a mold (34 and 36) has a first cavity (50) in which a first insert (52 and 53) is positioned, the first insert defining a length and a width of a package body which is to be formed in the mold. The first insert in the first cavity also defines a second cavity (54) in which a second insert (56 and 57) is positioned, the second insert defining a thickness of the package body. Plastic is inserted into the mold to form the package body. To form other package types, one or more inserts are replaced instead of using a different mold. In another embodiment, the inserts are adjustable. For example, rather than having to change inserts to form a package with a different thickness, the inserts are adjusted by, for instance, a screw mechanism (66) within the mold or by the addition or removal of shims (60).
    Type: Grant
    Filed: August 21, 1992
    Date of Patent: September 6, 1994
    Assignee: Motorola, Inc.
    Inventors: Michael B. McShane, Alan H. Woosley, Francis Primeaux
  • Patent number: 5233222
    Abstract: A semiconductor device (30) utilizes a lead frame (32) having a window-frame flag (36). An opening (44) within the flag creates an interior edge (46) which is tapered, preferably to an angle .phi. that is between 55.degree. and 65.degree.. The tapered interior edge reduces boundary-layer separation of a resin molding compound during formation of a resin package body (42). Thus, voids in the resin packaging material near the interior edge of the flag are less likely to be formed.
    Type: Grant
    Filed: July 27, 1992
    Date of Patent: August 3, 1993
    Assignee: Motorola, Inc.
    Inventors: Frank Djennas, Alan H. Woosley
  • Patent number: 4434360
    Abstract: A single optical fiber is placed at or near the nadir of the curvilinear section of the optical surface of a light emitting device. The LED element illuminates the bar code characters on the surface of the object being read, and the reflected light is transmitted up the optical fiber to a sensory means or the like. The elements are encased in an optical plastic medium for strength and durability, and resistance to environmental extremes.
    Type: Grant
    Filed: September 15, 1983
    Date of Patent: February 28, 1984
    Assignee: Texas Instruments Incorporated
    Inventors: Alan H. Woosley, Billy R. Masten