Abstract: A method for generating a graphical overlay indicating storage usage for a graphical representation of an information handling system includes determining a first storage capacity of a first hardware component of a second information handling system, determining a first storage usage of the first hardware component, generating a first graphical overlay for a first graphical representation of a physical configuration of the first information handling system based on the first storage capacity of the first hardware component and the first storage usage of the first hardware component, wherein the first graphical overlay comprises a first indication of the first storage usage of the first hardware component, and displaying the first graphical overlay and the first graphical representation.

Abstract: Techniques are described herein are related to managing deployment of a converged infrastructure (CI). Such techniques may include receiving a request to initiate a CI deployment; obtaining a CI information set; creating a CI deployment file using the CI information set; rendering a deployment user interface (UI) screen that allows a user to select to configure network devices or a CI cluster; receiving a first selection to configure a network device; rendering network device configuration screens to obtain network device configuration information; adding the network device configuration information to the CI deployment file; receiving a second selection to configure the CI cluster; rendering CI cluster configuration screens to obtain CI cluster configuration information; adding the CI cluster configuration information to the CI deployment file; and deploying the CI using the CI deployment file.

Abstract: A method for generating a graphical overlay indicating component characteristics for a graphical representation of an information handling system includes determining one or more component characteristics of one or more hardware components of a second information handling system, generating a first graphical overlay for a first graphical representation of a physical configuration of the one or more hardware components based on the one or more component characteristics, determining a selected view, and displaying the first graphical overlay and the first graphical representation based on the determination of the selected view.

Abstract: Techniques are described herein are related to managing deployment of a converged infrastructure (CI). Such techniques may include receiving a request to initiate a CI deployment; obtaining a CI information set; creating a CI deployment file using the CI information set; rendering a deployment user interface (UI) screen that allows a user to select to configure network devices or a CI cluster; receiving a first selection to configure a network device; rendering network device configuration screens to obtain network device configuration information; adding the network device configuration information to the CI deployment file; receiving a second selection to configure the CI cluster; rendering CI cluster configuration screens to obtain CI cluster configuration information; adding the CI cluster configuration information to the CI deployment file; and deploying the CI using the CI deployment file.

Abstract: A cache system includes a processor chip to receive a processing unit address. The cache system also includes a comparator to compare the processing unit address to an address information stored in an allocated tag subset of a tag memory of the processor chip to determine whether the processing unit address matches the address information. The cache system further includes a mapping device to map the portion of the address information to an external memory data, temporarily stored in an allocated data memory subset and a corresponding data memory set of a data memory in the processor. Furthermore, the cache system includes a stacking loop to prioritize the allocated tag subset and a corresponding tag set when the processing unit address matches the address information.

Abstract: A cache system includes a processor chip to receive a processing unit address. The cache system also includes a comparator to compare the processing unit address to an address information stored in in an allocated tag subset of a tag memory of the processor chip to determine whether the processing unit address matches the address information. The cache system further includes a mapping device to map the portion of the address information to an external memory data, temporarily stored in an allocated data memory subset and a corresponding data memory set of a data memory in the processor. Furthermore, the cache system includes a stacking loop to prioritize the allocated tag subset and a corresponding tag set when the processing unit address matches the address information.

Abstract: Methods and system of reducing power consumption of system on chip based on analog-to-digital control circuitry are disclosed. In one embodiment, a method includes converting an analog signal of external device coupled to the system on chip to a digital signal using an analog-to-digital converter (ADC) of the system on chip with a processor of the system on chip in a sleep mode or power down mode. The method further includes waking up the processor of the system on ship to perform an exception event based on a comparison of the digital signal with a threshold value associated with the external device.

Abstract: Systems, devices and methods for clearing memory using a built-in self-test circuit are disclosed. In one embodiment, a device for clearing memory using a built-in self-test circuit comprises a clear memory module added to a memory built-in self-test (MBIST) controller generating a signal for clearing one or more memory modules and one or more wrapper circuits with each wrapper circuit comprising an address generator module forwarding a range of addresses associated with the clearing the memory modules, a write data generator module forwarding a pattern of logical zeroes to the range of addresses and a finite state machine controlling writing the pattern to the range of addresses based on the signal for the clearing the memory modules.