Patents by Inventor Alan Hiroshi Ouye
Alan Hiroshi Ouye has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11195756Abstract: Methods of and carriers for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a cover ring for protecting a carrier and substrate assembly during an etch process includes an inner opening having a diameter smaller than the diameter of a substrate of the carrier and substrate assembly. An outer frame surrounds the inner opening. The outer frame has a bevel for accommodating an outermost portion of the substrate of the carrier and substrate assembly.Type: GrantFiled: September 19, 2014Date of Patent: December 7, 2021Assignee: Applied Materials, Inc.Inventors: James M. Holden, Alexander N. Lerner, Ajay Kumar, Aparna Iyer, Alan Hiroshi Ouye
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Patent number: 9478455Abstract: Methods of and apparatuses for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a shadow ring assembly for a plasma processing chamber includes an annular body including a thermally conductive material. The annular body includes a top surface to face an interior of the plasma chamber, and a bottom surface to face a substrate carrier in the plasma chamber. A plurality of posts are attached to the annular body and positioned substantially below the bottom surface of the annular body. Each of the plurality of posts includes an inner core of thermal pyrolytic graphite (TPG). The shadow ring assembly also includes a plasma resistant coating on the annular body and the plurality of posts.Type: GrantFiled: June 12, 2015Date of Patent: October 25, 2016Assignee: Applied Materials, Inc.Inventors: Alan Hiroshi Ouye, Alexander N. Lerner
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Patent number: 9378930Abstract: Embodiments of the present invention generally provide an inductively coupled plasma (ICP) reactor having a substrate RF bias that is capable of control of the RF phase difference between the ICP source (a first RF source) and the substrate bias (a second RF source) for plasma processing reactors used in the semiconductor industry. Control of the RF phase difference provides a powerful knob for fine process tuning. For example, control of the RF phase difference may be used to control one or more of average etch rate, etch rate uniformity, etch rate skew, critical dimension (CD) uniformity, and CD skew, CD range, self DC bias control, and chamber matching.Type: GrantFiled: March 4, 2010Date of Patent: June 28, 2016Assignee: APPLIED MATERIALS, INC.Inventors: Michael N. Grimbergen, Alan Hiroshi Ouye, Valentin N. Todorow
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Publication number: 20160086852Abstract: Methods of and carriers for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a cover ring for protecting a carrier and substrate assembly during an etch process includes an inner opening having a diameter smaller than the diameter of a substrate of the carrier and substrate assembly. An outer frame surrounds the inner opening. The outer frame has a bevel for accommodating an outermost portion of the substrate of the carrier and substrate assembly.Type: ApplicationFiled: September 19, 2014Publication date: March 24, 2016Inventors: James M. Holden, Alexander N. Lerner, Ajay Kumar, Aparna Iyer, Alan Hiroshi Ouye
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Patent number: 9293304Abstract: Methods of and apparatuses for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a plasma thermal shield for a plasma processing chamber includes an annular ring body having an inner opening. A plasma-facing surface of the annular ring body has a general topography. A bottom surface of the annular ring body reciprocates the general topography with recessed regions disposed therein, providing one or more protruding regions at the bottom surface of the annular ring body.Type: GrantFiled: December 17, 2013Date of Patent: March 22, 2016Assignee: Applied Materials, Inc.Inventor: Alan Hiroshi Ouye
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Patent number: 9236284Abstract: Methods of and apparatuses for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a tape frame lift assembly for a plasma processing chamber includes a capture single ring having an upper surface for supporting a tape frame of a substrate support and for cooling the tape frame. The tape frame lift assembly also includes one or more capture lift arms for moving the capture single ring to and from transfer and processing positions. The tape frame assembly also includes one or more captured lift plate portions, one captured lift plate portion corresponding to one capture lift arm, the one or more captured lift plate portions for coupling the one or more capture lift arms to the capture single ring.Type: GrantFiled: January 31, 2014Date of Patent: January 12, 2016Assignee: Applied Materials, Inc.Inventor: Alan Hiroshi Ouye
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Patent number: 9165812Abstract: Methods of and apparatuses for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a tape frame lift assembly for a plasma processing chamber includes a capture single ring having an upper surface for supporting a tape frame of a substrate support and for cooling the tape frame. The tape frame lift assembly also includes one or more capture lift arms for moving the capture single ring to and from transfer and processing positions. The tape frame assembly also includes one or more captured lift plate portions, one captured lift plate portion corresponding to one capture lift arm, the one or more captured lift plate portions for coupling the one or more capture lift arms to the capture single ring.Type: GrantFiled: March 19, 2014Date of Patent: October 20, 2015Assignee: Applied Materials, Inc.Inventor: Alan Hiroshi Ouye
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Publication number: 20150221553Abstract: Methods of and apparatuses for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a tape frame lift assembly for a plasma processing chamber includes a capture single ring having an upper surface for supporting a tape frame of a substrate support and for cooling the tape frame. The tape frame lift assembly also includes one or more capture lift arms for moving the capture single ring to and from transfer and processing positions. The tape frame assembly also includes one or more captured lift plate portions, one captured lift plate portion corresponding to one capture lift arm, the one or more captured lift plate portions for coupling the one or more capture lift arms to the capture single ring.Type: ApplicationFiled: January 31, 2014Publication date: August 6, 2015Inventor: Alan Hiroshi Ouye
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Publication number: 20150221539Abstract: Methods of and apparatuses for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a tape frame lift assembly for a plasma processing chamber includes a capture single ring having an upper surface for supporting a tape frame of a substrate support and for cooling the tape frame. The tape frame lift assembly also includes one or more capture lift arms for moving the capture single ring to and from transfer and processing positions. The tape frame assembly also includes one or more captured lift plate portions, one captured lift plate portion corresponding to one capture lift arm, the one or more captured lift plate portions for coupling the one or more capture lift arms to the capture single ring.Type: ApplicationFiled: March 19, 2014Publication date: August 6, 2015Inventor: Alan Hiroshi Ouye
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Publication number: 20150170885Abstract: Methods of and apparatuses for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a plasma thermal shield for a plasma processing chamber includes an annular ring body having an inner opening. A plasma-facing surface of the annular ring body has a general topography. A bottom surface of the annular ring body reciprocates the general topography with recessed regions disposed therein, providing one or more protruding regions at the bottom surface of the annular ring body.Type: ApplicationFiled: March 19, 2014Publication date: June 18, 2015Inventor: Alan Hiroshi Ouye
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Publication number: 20150170884Abstract: Methods of and apparatuses for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a plasma thermal shield for a plasma processing chamber includes an annular ring body having an inner opening. A plasma-facing surface of the annular ring body has a general topography. A bottom surface of the annular ring body reciprocates the general topography with recessed regions disposed therein, providing one or more protruding regions at the bottom surface of the annular ring body.Type: ApplicationFiled: December 17, 2013Publication date: June 18, 2015Applicant: APPLIED MATERIALS, INC.Inventor: Alan Hiroshi Ouye
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Publication number: 20150170955Abstract: Methods of and apparatuses for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a shadow ring assembly for a plasma processing chamber includes a shadow ring having an annular body and an inner opening. The shadow ring assembly further includes a cooling channel disposed in the annular body for cooling fluid transport. The cooling channel is coupled to a pair of supply/return openings at a surface of the annular body.Type: ApplicationFiled: December 17, 2013Publication date: June 18, 2015Applicant: Applied Materials, Inc.Inventors: Alan Hiroshi Ouye, Alexander N. Lerner
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Patent number: 8568553Abstract: A method and apparatus for etching photomasks is provided herein. In one embodiment, the apparatus comprises a process chamber having a support pedestal adapted for receiving a photomask. An ion-neutral shield is disposed above the pedestal and a deflector plate assembly is provided above the ion-neutral shield. The deflector plate assembly defines a gas flow direction for process gases towards the ion-neutral shield, while the ion-neutral shield is used to establish a desired distribution of ion and neutral species in a plasma for etching the photomask.Type: GrantFiled: March 10, 2011Date of Patent: October 29, 2013Assignee: Applied Materials, Inc.Inventors: Ajay Kumar, Madhavi R. Chandrachood, Richard Lewington, Darin Bivens, Amitabh Sabharwal, Sheeba J. Panayil, Alan Hiroshi Ouye
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Publication number: 20110236806Abstract: Methods for processing photomasks are provided herein. In some embodiments, a method for processing a photomask may include providing a photomask to a substrate support within a process chamber; providing a process gas to the process chamber having the photomask disposed therein; providing a negative or zero voltage to a substrate support cathode having the photomask disposed thereon; providing a source RF power to an anode coupled to the process chamber to ignite the process gas to form a plasma; and processing the photomask.Type: ApplicationFiled: October 8, 2010Publication date: September 29, 2011Applicant: APPLIED MATERIALS, INC.Inventors: ALAN HIROSHI OUYE, DARIN BIVENS, DAVID KNICK
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Publication number: 20110162797Abstract: A method and apparatus for etching photomasks is provided herein. In one embodiment, the apparatus comprises a process chamber having a support pedestal adapted for receiving a photomask. An ion-neutral shield is disposed above the pedestal and a deflector plate assembly is provided above the ion-neutral shield. The deflector plate assembly defines a gas flow direction for process gases towards the ion-neutral shield, while the ion-neutral shield is used to establish a desired distribution of ion and neutral species in a plasma for etching the photomask.Type: ApplicationFiled: March 10, 2011Publication date: July 7, 2011Inventors: Ajay Kumar, Madhavi R. Chandrachood, Richard Lewington, Darin Bivens, Amitabh Sabharwal, Sheeba J. Panayil, Alan Hiroshi Ouye
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Patent number: 7943005Abstract: A method and apparatus for etching photomasks is provided herein. In one embodiment, the apparatus comprises a process chamber having a support pedestal adapted for receiving a photomask. An ion-neutral shield is disposed above the pedestal and a deflector plate assembly is provided above the ion-neutral shield. The deflector plate assembly defines a gas flow direction for process gases towards the ion-neutral shield, while the ion-neutral shield is used to establish a desired distribution of ion and neutral species in a plasma for etching the photomask.Type: GrantFiled: October 30, 2006Date of Patent: May 17, 2011Assignee: Applied Materials, Inc.Inventors: Ajay Kumar, Madhavi R. Chandrachood, Richard Lewington, Darin Bivens, Amitabh Sabharwal, Sheeba J. Panayil, Alan Hiroshi Ouye
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Patent number: 7909961Abstract: A method and apparatus for etching photomasks are provided herein. The apparatus includes a process chamber with a shield above a substrate support. The shield comprises a plate with apertures, and the plate has two zones with at least one characteristic, such as material or potential bias, that is different from each other. The method provides for etching a photomask substrate with a distribution of ions and neutral species that pass through the shield.Type: GrantFiled: October 30, 2006Date of Patent: March 22, 2011Assignee: Applied Materials, Inc.Inventors: Ajay Kumar, Madhavi R. Chandrachood, Richard Lewington, Darin Bivens, Amitabh Sabharwal, Sheeba J. Panayil, Alan Hiroshi Ouye
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Publication number: 20100276391Abstract: Methods of operating inductively coupled plasma (ICP) reactors having ICP sources and substrate bias with phase control are provided herein. In some embodiments, a method of operating a first plasma reactor having a source RF generator inductively coupled to the first plasma reactor on one side of a substrate support surface of a substrate support within the first plasma reactor and a bias RF generator coupled to the substrate support on an opposing side of the substrate support surface, wherein the source RF generator and the bias RF generator provide respective RF signals at a common frequency may include selecting a desired value of a process parameter for a substrate to be processed; and adjusting the phase between respective RF signals provided by the source RF generator and the bias RF generator to a desired phase based upon a predetermined relationship between the process parameter and the phase.Type: ApplicationFiled: March 29, 2010Publication date: November 4, 2010Applicant: APPLIED MATERIALS, INC.Inventors: MICHAEL N. GRIMBERGEN, KEVEN KAISHENG YU, ALAN HIROSHI OUYE, MADHAVI R. CHANDRACHOOD, VALENTIN N. TODOROW, TOI YUE BECKY LEUNG, RICHARD LEWINGTON, DARIN BIVENS, RENEE KOCH, IBRAHIM M. IBRAHIM, AMITABH SABHARWAL, AJAY KUMAR
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Publication number: 20100224321Abstract: Embodiments of the present invention generally provide an inductively coupled plasma (ICP) reactor having a substrate RF bias that is capable of control of the RF phase difference between the ICP source (a first RF source) and the substrate bias (a second RF source) for plasma processing reactors used in the semiconductor industry. Control of the RF phase difference provides a powerful knob for fine process tuning. For example, control of the RF phase difference may be used to control one or more of average etch rate, etch rate uniformity, etch rate skew, critical dimension (CD) uniformity, and CD skew, CD range, self DC bias control, and chamber matching.Type: ApplicationFiled: March 4, 2010Publication date: September 9, 2010Applicant: APPLIED MATERIALS, INC.Inventors: MICHAEL N. GRIMBERGEN, ALAN HIROSHI OUYE, VALENTIN N. TODOROW
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Publication number: 20090220865Abstract: A method and apparatus for improved plasma etching uniformity are provided herein. In one embodiment, a field-shaping magnet is disposed above the chamber processing volume and adjacent to field induction coils. The field-shaping magnet provides improved control of the etch rate at various locations along the surface of a substrate by providing adjustability in the radial profile of a plasma-producing electric field generated by the induction coils. In another embodiment, two field-shaping magnets are used to improve etching uniformity at the substrate surface.Type: ApplicationFiled: February 29, 2008Publication date: September 3, 2009Inventor: ALAN HIROSHI OUYE