Abstract: A computer and its corresponding cache system includes a cache memory, a buffer unit, and a bus transaction queue. The buffer unit includes a plurality of entries suitable for temporarily storing data, address, and attribute information of operations generated by the CPU. A first operation initiated by the load store unit buffers an operation in a first entry of the buffer unit, which initiates a first transaction to be queued in a first entry of the bus transaction queue where the first transaction in the bus transaction queue points to the first entry in the buffer unit. Preferably, the buffer unit is configured to modify the first transaction from a first transaction type to a second transaction type prior to execution in response to an event that alters the data requirements of the queued transaction. Additional utility is achieved by merging multiple store operation that miss to a common cache line into a single entry.

Abstract: A method and system in an information processing system are disclosed for efficiently maintaining copies of values stored within a plurality of registers. The information processing system includes first circuitry, second circuitry, and a plurality of buffers. The first circuitry processes an execution state of a first type of instruction which always specifies a destination of at least one of a first type of register or a second type of register, and which outputs first information in response thereto. The first circuitry also processes an execution stage of a second type of instruction which always specifies a destination of only a third type of register, and outputs second information in response thereto.

Abstract: The present invention relates to the monitoring of current drawn by an ignition coil for a spark ignition engine, and in particular to circuitry and a method for detecting a malfunction in the charging of an ignition coil or its associated drive circuitry. The electronic circuit comprises: circuitry to measure the voltage of a battery (VB) for charging the coil; software (52) to determine according to the measured battery voltage (VB) a nominal dwell time (TC) for charging fully the coil prior to discharge of the coil; circuitry (32,34) to measure an amount of current drawn by the coil over a time less than the time taken to charge fully the coil; software (36) to extrapolate from the measured current a calculated expected dwell time TD to charge fully the coil; and a device to indicate an error condition (44,62,64,66,68) if the difference (44) between the expected (TD) and nominal (TC) dwell times is beyond a predetermined error limit (58,60).

Abstract: The present invention relates to apparatus for scheduling the ignition sparks for a spark ignition internal combustion engine. An ignition system for a spark ignition engine, includes a device for generating a series of pulses (12) upon each revolution of a crankshaft (1) and a device (8,118) for identifying pulses in the series relative to a top dead center position (TDC) for the engine, one or more ignition coils and a device to charge a coil and then to discharge the coil to generate an ignition spark at a desired spark angle (54) relative to the top dead center position (TDC). The ignition system identifies a first particular pulse (60) occurring after the charging starts and before the discharging begins, and calculates a first interval (I.sub.D) from the first particular pulse (60) so that the discharging happens proximate the desired spark angle (54).

Abstract: A method and system for dynamically recovering a lookahead register-address-table (RAT) in a processor that executes program instructions. Each instruction that updates a logical register address is assigned to a different physical register address. Each of the instructions to be processed by the processor are stored in a fifo queue. The physical register address assignments for each of the instructions are stored in a first RAT, and information regarding instructions that have completed execution by the processor are stored in a second RAT. The method and system further comprises storing the physical register address assignments for non-branch instructions from the fifo queue in a recovery RAT. The first RAT is then restored after an interrupt occurs by copying the second RAT into the recovery RAT and then copying the recovery RAT into the first RAT.

Abstract: A method and system in a data processing system are disclosed for efficiently handling exceptions. The data processing system includes a register for storing indications of multiple instructions while the multiple instructions are being concurrently processed. An exception is generated within the data processing system. A determination is made whether the exception was generated by one of the multiple instructions. In response to a determination that one of the multiple instructions generated the exception, a determination is then made whether an indication of the instruction which generated the exception is stored in a particular position within a register within the data processing system. In response to a determination that the indication of the instruction is stored in the particular position within the register, the exception is associated with a first priority group.

Abstract: A method and system in a data processing system are disclosed for efficiently managing an indication of a status of each of a plurality of registers included with the data processing system. An array is established having multiple entry fields for storing multiple entries. Each of the multiple entry fields is associated with a different one of the plurality of registers. A status of each of the plurality of registers is determined. A plurality of partitions are established within the array. Each of the partitions are concurrently accessible by the data processing system. A plurality of the multiple entry fields are associated with one of the plurality partitions. An entry is stored in each of the multiple entry field. The entry includes the status of each of the plurality of registers. Each entry is associated with one of the partitions so that a plurality of the multiple entries may be concurrently accessed.