Abstract: The disclosure describes a memory system having a large bit capacity, capable of detecting, locating, and correcting errors. The memory is subdivided into several identical storage matrices wherein parity calculations are performed in the vertical direction within a matrix and in the horizontal direction across a series of matrices. The system also has provision for self-repairs.

Abstract: An error correction system is provided for a random access memory system of the magnetic core or plated wire type, and which serves to render the memory system immune to the effects of nuclear radiation, and the like. The system of the invention includes circumvent circuitry which serves to limit all currents in the memory access network to safe values during a radiation event, so as to pevent burn-out of the memory and of its associated components. The system of the invention also serves to correct single word errors which can occur to words being written or read during the radiation pulse. The single word error correction is achieved in a first embodiment of the invention by partitioning the fixed data program words in the memory into blocks; by providing an error correction word for each such block, and by reconstructing from the error correction word, the word being read or written during the radiation pulse.