Abstract: A circuit having an amplifier, comprising: a depletion mode transistor having a source electrode coupled to a reference potential; a drain electrode coupled to a potential more positive than the reference potential; and a gate electrode for coupling to an input signal. The circuit includes a bias circuit, comprising: a current source; and biasing circuitry coupled to the current source and between the potential more positive than the reference potential and a potential more negative than the reference potential. A control circuit is connected to the current source for controlling the amount of current produced by the current source to the biasing circuitry.

Abstract: An amplifier having a Radio Frequency (RF) power level detector circuit for producing a control signal in accordance with a power level of an RF input signal. The control signal indicates whether the power level of the input signal is within a predetermined range of power levels greater than zero. A bias circuit is fed by the control signal, for producing a fixed bias voltage at a gate electrode of a field effect transistor (FET) to establish a predetermined quiescent current for the FET when the control signal indicates the power level of the RF input signal is within the predetermined range of power levels and to reduce the bias voltage to reduce the predetermined quiescent current when the control signal indicates the power level of the RF input signal is below the predetermined range of power levels.

Abstract: An amplifier having a Radio Frequency (RF) power level detector circuit for producing a control signal in accordance with a power level of an RF input signal. The control signal indicates whether the power level of the input signal is within a predetermined range of power levels greater than zero. A bias circuit is fed by the control signal, for producing a fixed bias voltage at a gate electrode of a field effect transistor (FET) to establish a predetermined quiescent current for the FET when the control signal indicates the power level of the RF input signal is within the predetermined range of power levels and to reduce the bias voltage to reduce the predetermined quiescent current when the control signal indicates the power level of the RF input signal is below the predetermined range of power levels.

Abstract: A Field Effect Transistor (FET) having a substrate; a plurality of active regions disposed on the substrate; and a laterally extending finger-like control electrode disposed on a portion of a surface of the substrate. The active regions are laterally spaced one from the other successively along the laterally extending finger-like control electrode. The laterally extending finger-like control electrode controls a flow of carriers through each one of the plurality of active regions between a source electrode and a drain electrode.

Abstract: A circuit having an amplifier, comprising: a depletion mode transistor having a source electrode coupled to a reference potential; a drain electrode coupled to a potential more positive than the reference potential; and a gate electrode for coupling to an input signal. The circuit includes a bias circuit, comprising: a current source; and biasing circuitry coupled to the current source and between the potential more positive than the reference potential and a potential more negative than the reference potential. A control circuit is connected to the current source for controlling the amount of current produced by the current source to the biasing circuitry.

Abstract: A Field Effect Transistor (FET) having a substrate; a plurality of active regions disposed on the substrate; and a laterally extending finger-like control electrode disposed on a portion of a surface of the substrate. The active regions are laterally spaced one from the other successively along the laterally extending finger-like control electrode. The laterally extending finger-like control electrode controls a flow of comers through each one of the plurality of active regions between a source electrode and a drain electrode.

Abstract: A circuit having an amplifier, comprising: a depletion mode transistor having a source electrode coupled to a reference potential; a drain electrode coupled to a potential more positive than the reference potential; and a gate electrode for coupling to an input signal. The circuit includes a bias circuit, comprising: a current source; and biasing circuitry coupled to the current source and between the potential more positive than the reference potential and a potential more negative than the reference potential. A control circuit is connected to the current source for controlling the amount of current produced by the current source to the biasing circuitry.

Abstract: A microwave amplifier having a field effect transistor formed on an upper surface of a substrate. A de-Q'ing section connected to the field effect transistor includes: a de-Q'ing resistive via that passes through the substrate; and a de-Q'ing capacitor having one plate thereof connected a ground plane conductor through the de-Q'ing resistive via.

Abstract: A high power RF connector receptacle having a solderable pin, an outer connector receptacle shell and a high breakdown voltage dielectric such as Silicon Carbide. The connector receptacle can be completed as a stepped process where the Silicon Carbide substrate can be mounted to the package, the pin can be dropped into place and soldered, and then the outer shell can be soldered onto the SiC substrate. Alternatively, the SiC, pin and outer shell can be assembled as a subassembly and then soldered to the package. The combination of SiC and solder gives a hermetic seal to the package. In addition, the SiC has an extraordinarily high dielectric breakdown voltage for high power connections.

Abstract: A Field Effect Transistor (FET) having a plurality of FET cells having a plurality of source pads, a plurality of drain pads, and a plurality of gate electrodes disposed on a surface of a substrate; each one of the FET cells having a corresponding one of the gate electrodes disposed between one of the source pads and one of the drain pads. The FET includes; a gate contact connected to the gate electrode of each one of the FET cells; a drain contact connected to the drain pad of each one of the FET cells; and a source contact connected to source pad of each one of the FET cells. The cells are disposed in a loop configuration.

Abstract: A Field Effect Transistor (FET) having: a plurality of FET cells having a plurality of source pads, a plurality of drain pads, and a plurality of gate electrodes disposed on a surface of a substrate; each one of the FET cells having a corresponding one of the gate electrodes disposed between one of the source pads and one of the drain pads; a gate contact connected to the gate electrodes of each one of the FET cells; a drain contact connected to the drain pad of each one of the FET cells; and a source contact connected to source pad of each one of the FET cells. The cells are disposed on a surface in a two-dimensional array.

Abstract: A high power RF connector receptacle having a solder able pin, an outer connector receptacle shell and a high breakdown voltage dielectric such as Silicon Carbide. The connector receptacle can be completed as a stepped process where the Silicon Carbide substrate can be mounted to the package, the pin can be dropped into place and soldered, and then the outer shell can be soldered onto the SiC substrate. Alternatively, the SiC, pin and outer shell can be assembled as a subassembly and then soldered to the package. The combination of SiC and solder gives a hermetic seal to the package.

Abstract: A Microwave Monolithic Integrated Circuit (MMIC) having an integrated high power load. The MMIC includes a microwave transmission line and a resistive load coupled to a terminating end of the microwave transmission line. The resistive load comprises a hollow resistive material disposed on sidewalls of a via passing through a substrate, the resistive material having an upper portion electrically connected to a terminating end of a strip conductor of the microwave transmission line strip conductor and a lower portion electrically connected to the ground plane.

Abstract: A Field Effect Transistor (FET) having a plurality of FET cells having a plurality of source pads, a plurality of drain pads, and a plurality of gate electrodes disposed on a surface of a substrate; each one of the FET cells having a corresponding one of the gate electrodes disposed between one of the source pads and one of the drain pads. The FET includes; a gate contact connected to the gate electrode of each one of the FET cells; a drain contact connected to the drain pad of each one of the FET cells; and a source contact connected to source pad of each one of the FET cells. The cells are disposed in a loop configuration.

Abstract: A Field Effect Transistor (FET) having: a plurality of FET cells having a plurality of source pads, a plurality of drain pads, and a plurality of gate electrodes disposed on a surface of a substrate; each one of the FET cells having a corresponding one of the gate electrodes disposed between one of the source pads and one of the drain pads; a gate contact connected to the gate electrodes of each one of the FET cells; a drain contact connected to the drain pad of each one of the FET cells; and a source contact connected to source pad of each one of the FET cells. The cells are disposed on a surface in a two-dimensional array.

Abstract: A circuit having an amplifier, comprising: a depletion mode transistor having a source electrode coupled to a reference potential; a drain electrode coupled to a potential more positive than the reference potential; and a gate electrode for coupling to an input signal. The circuit includes a bias circuit, comprising: a current source; and biasing circuitry coupled to the current source and between the potential more positive than the reference potential and a potential more negative than the reference potential. A control circuit is connected to the current source for controlling the amount of current produced by the current source to the biasing circuitry.

Abstract: An attenuator module having an attenuator disposed on a top surface of a substrate, an input terminal at one end of the attenuator and an output terminal at an opposite end of the attenuator. A pair of spaced electrical conductor pads is disposed on a bottom surface of the substrate, a first one of the pads being disposed under the input terminal and a second one of the pads being disposed under the output terminal. A pair of conductive vias passes through the substrate, one conductive via connecting the input terminal to the first one of the pads and the other conductive via connecting the output terminal to the second one of the pads. The module may be used to interconnect two adjacent circuit substrates.

Abstract: An attenuator module having an attenuator disposed on a top surface of a substrate, an input terminal at one end of the attenuator and an output terminal at an opposite end of the attenuator. A pair of spaced electrical conductor pads is disposed on a bottom surface of the substrate, a first one of the pads being disposed under the input terminal and a second one of the pads being disposed under the output terminal. A pair of conductive vias passes through the substrate, one conductive via connecting the input terminal to the first one of the pads and the other conductive via connecting the output terminal to the second one of the pads. The module may be used to interconnect two adjacent circuit substrates.

Abstract: A power sensor having a microstrip transmission line, comprising: a dielectric substrate; a strip conductor disposed on one surface of the substrate; and a ground plane conductor disposed on an opposite surface of the substrate. The power sensor includes a plurality of thermocouples extending from the strip conductor, proximal end portions of the thermocouples being thermally coupled to the strip conductor. A plurality of electrical conductors is provided, each one having a first end electrically connected to a distal end of a corresponding one of the thermocouples and a second end electrically connected to the proximate end of one of the plurality of thermocouples disposed adjacent to such corresponding one of the thermocouples. The proximal ends of the thermocouples are electrically insulated one from the other.