Abstract: A memory having an address generator in an intelligent port which generates address sequences specified by an array transformation operator in a programmable processor, thereby allowing a controlling processor to proceed immediately to the preparation of the next instruction in parallel with memory execution of a present instruction. The intelligent port of the memory creates complex data structures from input data arrays stored in memory and directs the transformation of the data structures into output data streams. The memory comprises a plurality of read-write memory banks and a bank of read-only memory interconnected through intelligent ports and busses to other units of the processor. An arbitration and switching network assigns memory banks to the intelligent ports.

Abstract: A memory having an address generator which generates nested address sequences specified by an array transformation operator in a programmable processor, thereby allowing a controlling processor to proceed immediately to the preparation of the next instruction in parallel with memory execution of a complex present instruction. The address generator generates row and column indices specified by the array transformation operator comprising an initial reference point parameter, a boundary parameter and a plurality of displacement and length parameters expressed relative to the initial reference point. Address sequences for data representing a vector, matrix, or block are generated in a single memory in accordance with the factored series of nested addressing sequences specified by the array transformation.

Abstract: An arrangement is shown for controlling transmission of blocks of information to and from a plurality of major components of a digital computer system interconnected by common buses. The disclosed arrangement operates so that any component of the system may normally seize, on a nonpriority basis, one of the buses at the beginning of any time slot defined by two successive clock pulses generated by a single source and applied to all components simultaneously; however, if a special instruction is encountered during execution of a program, any component may retain a bus for more than one time slot. The disclosed arrangement also permits error checking of transmitted information from a given major component without interfering with transmission from any other major component and automatically causes retransmission of any block of information found to be improperly transmitted originally.