Abstract: A technique for providing a partial memory of one half of the possible storage bits comprised of any two quadrants is implemented by decoupling the one of four decoder used for normal operation and providing a programmable decoder which is capable of being programmed to select one of any two quadrants. If only one quadrant is to form the partial memory, the programmable decoder can be programmed to select only one latch. In another embodiment, a decoder is provided which can also be programmed to select one of any three quadrants.

Abstract: A serial data mode circuit, which provides valid data on a falling edge of a data valid signal, uses time between falling edges to prepare for the next falling edge in order to reduce the time between when a falling edge of the data valid signal occurs and when data actually becomes valid. A plurality of interconnected flip-flops selectively enable data latches containing data in response to a rising edge of the data valid signal. The data is then provided to a tri-state driver prior to the falling edge of the data valid signal. The tri-state driver is then enabled in response to the falling edge of the data valid signal.