Abstract: Systems, methods and apparatuses to log memory errors in memory devices that can perform wear leveling based on physical addresses used in the memory devices to address select memory cells. For example, a controller of a memory sub-system communicates with a memory device installed in the memory sub-system to access memory cells in the memory device. During the communication to access memory cells in the memory device, the controller can determine a memory error at a first address. If the controller transmits the first address to the memory device for memory access at the time of the memory error, the memory device converts the first address to a second address to perform the memory access. The controller can be configured to determine the second address and record, in an error log, the memory error in association with the second address.

Abstract: Systems, methods, and apparatuses are provided for wear leveling repair in a memory device. A host is configured to issue a wear leveling command and a repair request to a memory device configured to check source data in a memory of the memory device for errors in response to receiving the wear leveling command from the host, transfer source data in the memory of the memory device to a target page, and repair a source page if the source data includes an error. The memory device is further configured to set a new repair match if a wear leveling repair element was not consumed after receiving the repair request and flush a previous repair match before setting the new repair match if the wear leveling repair element was consumed and a physical address of an incoming repair request is associated with the wear leveling repair element.

Abstract: A system for providing memory management holding latch placement and control signal generation is disclosed. The system performs memory management operations on a memory device to reduce memory cell wear and tear and to balance use of the memory cells of the memory device. The system separates memory management read operations from memory management write operations by utilizing a holding register that stores data from a source memory cell prior to transfer to a target memory cell. When a memory management read operation is initiated, data and error correction parity bits from the source memory cell are provided to a circuit including the holding register. The data and parity bits are analyzed for errors and the errors are corrected prior to storing the data and parity bits into the holding register. The data and associated parity bits are then transferred from the holding register to the target memory cell.

Abstract: Methods, systems, and devices for retiring pages of a memory device are described. An ordered set of device information pages may be used to store device information. The device information pages may be in non-volatile memory. Each page may include a counter value of the number of accesses to indicate if the page includes valid data. A flag associated with the page may be set when the counter value reaches a threshold, to retire the page. Upon power-up, the device may determine which page to use, based on the flags. The flag may be stored in the page, or may be separate (e.g., fuse elements). If fuse elements are used, the page may store a programming-in-process flag to indicate when programming of the fuse element may not have been completed before power loss, in which case the programming may be restarted after power is restored.

Abstract: Methods, systems, and devices for memory row-hammer mitigation are described. A memory device may operate based on a scheme that is continuous across power cycles. For example, the memory device may access a region if a value of a counter does not satisfy a threshold value and may access the region if a value of the counter satisfies the threshold value. Upon transitioning power states, the value of the counter may be stored to a non-volatile memory such that it may be accessed when transitioning back to the original power state (e.g., an “ON” state). Accordingly, the value of the counter may be maintained across power cycles.

Abstract: Methods, systems, and devices for techniques for non-volatile data protection are described. As part of a power on operation, a non-volatile memory system may be configured to selectively stored data. For example, the memory system may determine whether a host system is authorized to access data stored in the memory system prior to a power off operation. If the memory system determines that the host system is authorized, the memory device may retain the data. If the memory system determines that the host system is not authorized, the memory system may erase all or a portion of the data. In some cases, the memory system may maintain a retain flag to determine whether the host system is authorized. Additionally or alternatively, the memory system may determine whether a password received from the host system is valid to determine whether the host system is authorized.

Abstract: In accordance with some embodiments, a method is performed at a device with one or more processors, non-transitory memory, a display, and an input device. The method includes displaying, on the display, a playback status indicator regarding playback of a media item. The method includes displaying, on the display, an image associated with the media item. The method includes detecting an input interacting with the image. In response to a first portion of the input, the method includes adjusting the appearance of the image on the display in accordance with the first portion of the input. In response to a second portion of the input, the method includes changing playback of media items on the device in accordance with the input in accordance with the second portion of the input.

Abstract: Methods, systems, and devices for repair operation techniques are described. A memory device may detect a failure of a read operation associated with a physical row address of a memory die. The memory device may store information associated with the physical row address before performing a media management operation and after detecting the failure. Additionally or alternatively, the memory device may initiate a counter based on detecting the failure and may increment a value of the counter for each media management operation performed after detecting the failure. The memory device may send a command or other information to perform a repair operation for the physical row address. The memory device may determine the physical row address for the repair operation (e.g., despite media management operations) based on the stored information or the value of the counter, and may perform the repair operation on the physical row address.

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for soft post-package repair (SPPR). After packaging, it may be necessary to perform post-package repair operations on rows of the memory. During a scan mode of an SPPR operation, addresses provided by a fuse bank may be examined to determine if they are open addresses or if the bad row of memory is a redundant row of memory. The open addresses and the bad redundant addresses may be stored in volatile storage elements, such as in latch circuits. During a soft send mode of a SPPR operation, the address previously associated with the bad row of memory may be associated with the open address instead, and the address of the bad redundant row may be disabled.

Abstract: A memory device for extending addressable array space by incorporating virtual and physical memory arrays is disclosed. When extra storage space beyond a physical memory array is needed by a controller of the memory device, the storage space may be provided by extending the address space using a virtual array. The memory device incorporates the use of an extra row address bit to increase the addressable space, whereby the extra bit is utilized to address virtual rows in the virtual array. Spare or redundant physical memory elements utilized for memory repair may be programmed to a virtual address space for the virtual memory array. When a memory device operation is activated, the extra row address bit is set to high, and the virtual row address matches with a spare or redundant memory element, the virtual row in the virtual array space is activated for performance of the operation.

Abstract: Methods, systems, and devices for memory row-hammer mitigation are described. A memory device may operate based on a scheme that is continuous across power cycles. For example, the memory device may access a region if a value of a counter does not satisfy a threshold value and may access the region if a value of the counter satisfies the threshold value. Upon transitioning power states, the value of the counter may be stored to a non-volatile memory such that it may be accessed when transitioning back to the original power state (e.g., an “ON” state). Accordingly, the value of the counter may be maintained across power cycles.

Abstract: Methods, systems, and devices for techniques for non-volatile data protection are described. As part of a power on operation, a non-volatile memory system may be configured to selectively stored data. For example, the memory system may determine whether a host system is authorized to access data stored in the memory system prior to a power off operation. If the memory system determines that the host system is authorized, the memory device may retain the data. If the memory system determines that the host system is not authorized, the memory system may erase all or a portion of the data. In some cases, the memory system may maintain a retain flag to determine whether the host system is authorized. Additionally or alternatively, the memory system may determine whether a password received from the host system is valid to determine whether the host system is authorized.

Abstract: Systems, methods and apparatuses to log memory errors in memory devices that can perform wear leveling based on physical addresses used in the memory devices to address select memory cells. For example, a controller of a memory sub-system communicates with a memory device installed in the memory sub-system to access memory cells in the memory device. During the communication to access memory cells in the memory device, the controller can determine a memory error at a first address. If the controller transmits the first address to the memory device for memory access at the time of the memory error, the memory device converts the first address to a second address to perform the memory access. The controller can be configured to determine the second address and record, in an error log, the memory error in association with the second address.

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for automatic soft post-package repair (ASPPR). A memory may receive a row address along with a signal indicating an ASPPR operation, such as a bad page flag being set. A word line engine generates a physical address based on the row address, and ASPPR registers stores the physical address. The time it takes from receiving the row address to storing the physical address may be within the timing of an access operation on the memory such as tRAS. The row address may specify a single page of information. If the bad page flag is set, then a subsequent PPR operation may blow fuses to encode the physical address stored in the ASPPR registers.

Abstract: Methods, systems, and devices for retiring pages of a memory device are described. An ordered set of device information pages may be used to store device information. The device information pages may be in non-volatile memory. Each page may include a counter value of the number of accesses to indicate if the page includes valid data. A flag associated with the page may be set when the counter value reaches a threshold, to retire the page. Upon power-up, the device may determine which page to use, based on the flags. The flag may be stored in the page, or may be separate (e.g., fuse elements). If fuse elements are used, the page may store a programming-in-process flag to indicate when programming of the fuse element may not have been completed before power loss, in which case the programming may be restarted after power is restored.

Abstract: Methods, systems, and devices for modifying subsets of memory bank operating parameters are described. First global trimming information may be configured to adjust a first subset of operating parameters for a set of memory banks within a memory system. Second global trimming information may be configured to adjust a second subset of operating parameters for the set of memory banks. Local trimming information may be used to adjust one of the subsets of the operating parameters for a subset of the memory banks. To adjust one of the subsets of the operating parameters, the local trimming information may be combined with one of the first or second global trimming information to yield additional local trimming information that is used to adjust a corresponding subset of the operating parameters at the subset of the memory banks.

Abstract: Methods, systems, and devices for repair operation techniques are described. A memory device may detect a failure of a read operation associated with a physical row address of a memory die. The memory device may store information associated with the physical row address before performing a media management operation and after detecting the failure. Additionally or alternatively, the memory device may initiate a counter based on detecting the failure and may increment a value of the counter for each media management operation performed after detecting the failure. The memory device may send a command or other information to perform a repair operation for the physical row address. The memory device may determine the physical row address for the repair operation (e.g., despite media management operations) based on the stored information or the value of the counter, and may perform the repair operation on the physical row address.

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for automatic soft post-package repair (ASPPR). A memory may receive a row address along with a signal indicating an ASPPR operation, such as a bad page flag being set. A word line engine generates a physical address based on the row address, and ASPPR registers stores the physical address. The time it takes from receiving the row address to storing the physical address may be within the timing of an access operation on the memory such as tRAS. The row address may specify a single page of information. If the bad page flag is set, then a subsequent PPR operation may blow fuses to encode the physical address stored in the ASPPR registers.

Abstract: Techniques are provided for storing a row address of a defective row of memory cells to a bank of non-volatile storage elements (e.g., fuses or anti-fuses). After a memory device has been packaged, one or more rows of memory cells may become defective. In order to repair (e.g., replace) the rows, a post-package repair (PPR) operation may occur to replace the defective row with a redundant row of the memory array. To replace the defective row with a redundant row, an address of the defective row may be stored (e.g., mapped) to an available bank of non-volatile storage elements that is associated with a redundant row. Based on the bank of non-volatile storage elements the address of the defective row, subsequent access operations may utilize the redundant row and not the defective row.