Abstract: A pipelined linear array of processor elements (PEs) for performing matrix computations in an efficient manner. The linear array generally includes a head PE and a set of regular PEs, the head PE being a functional superset of the regular PE, with interconnections between nearest neighbor PEs in the array and a feedback path from a non-neighbor regular PE back to the head PE. Each PE includes arithmetic circuitry for performing multiply, combine and accumulate operations, and a register file for storing inputs and outputs of the arithmetic circuitry. The head PE further includes a non-linear function generator. Each PE is pipelined such that the latency for an arithmetic operation to complete is a multiple of the period with which new operations can be initiated. A Very Large Instruction Word (VLIW) program or other type of program may be used to control the array. The array is particularly efficient at performing complex matrix operations, such as, e.g.

Abstract: A digital circuit for computing a function consisting of sums and differences of the products of a first vector of N multipliers and a second vector of M multiplicands, where at least one of N and M is greater than one include N multibit recoding circuits and M multiples generator circuits. Each recoding circuit receives a respective multiplier as input and produces a radix-2k signed digit representation of the multiplier as output. Each multiples generator receives a respective multiplicand as input and producing multiples of the multiplicand between one and 2k−1 as output. The output of N recoding circuits and M multiples generator circuits are fed to an N×M array of partial product summers. Each partial product summer produces a respective product output, the set of outputs of the partial product summers comprising the product of each of the multipliers with each of the multiplicands.

Abstract: An application-specific single chip digital processor having flexible design expansion capability with minimal impact on the performance of a processor core. The processor core has an ALU and a register file (accumulators). The output of the ALU is connected to a multiplexer whose output is connected to the input of the register file. The output of the register file connects to one input of the ALU. A function unit, separate from the core, has an input connected to the output of the register file and an output connected to another input to the multiplexer. The core operates with a predefined instruction set. The function unit, which may be redesigned depending on the application, operates with a reserved (uncommitted) instruction set under control of the core.

Abstract: An integrated circuit including a circuit for improved efficiency of internal data transfer comprises: a processor core having a buffer memory; a random access memory having a read and write cycle time of a one clock cycle, the random access memory comprising a memory array with a predetermined word width and a data latch coupled to the memory array; a bi-directional data bus coupling the processor core to the random access memory, the bi-directional data bus having a data width which is a multiple of at least one times the predetermined word width; and, a signal circuit coupled to the data latch wherein the data latch is responsive to the signal circuit to latch data from the bi-directional data bus prior to writing the data to the memory array, wherein alternately reading two consecutive data words and writing two consecutive words occurs on an average in the clock cycle.

Abstract: An application-specific single chip digital processor having flexible design expansion capability with minimal impact on the performance of a processor core. The processor core has an ALU and a register file (accumulators). The output of the ALU is connected to a multiplexer whose output is connected to the input of the register file. The output of the register file connects to one input of the ALU. A function unit, separate from the core, has an input connected to the output of the register file and an output connected to another input to the multiplexer. The core operates with a predefined instruction set. The function unit, which may be redesigned depending on the application, operates with a reserved (uncommitted) instruction set under control of the core.

Abstract: There is disclosed an integrated circuit including a digital processor having EEPROM and a control register. The digital processor is capable of receiving data to be programmed into the EEPROM and is capable of programming the data into the EEPROM. The digital processor includes a control register for receiving bits to control a write line and an erase line. The digital processor also includes a processor core coupled to the control register by a data bus, the digital processor is coupled to the EEPROM by a ROM address bus and a RAM data bus. The EEPROM memory location identified by the ROM address bus is programmed to retain data latched onto the RAM data bus. This is achieved by the digital processor writing control bits to the control register to enable the write line for a write operation of sufficient duration to assure that the data on the RAM data bus is retained in the EEPROM memory address that is enabled.