Abstract: A controller for use in an optical storage device is provided. The controller includes a block decoder/encoder for processing data to and from a media of the optical storage device. An ATAPI interface is also provided and is configured to process data and control signals for selectively communicating data to and from the optical storage device during operation in an ATAPI mode. Universal serial bus (USB) logic is configured to process data and control signals for selectively communicating data to and from the optical storage device during operation in a USB mode. The USB logic is configured to utilize data transfer control logic implemented by the ATAPI interface. Accordingly, the one controller can be integrated into either an external peripheral device that communicates over a USB connection in the USB mode, or into an internal peripheral device that communicates over an IDE connection in the ATAPI mode.

Abstract: A receiver interface for interfacing with an Advanced Technology Attachment Packet Interface (ATAPI) in a first device. The receiver interface includes a converter, a depacketizing circuit, and an ATAPI receiver circuit. The converter converts a first set of signals from a serial bus into a second set of signals. The first set of signals are serial to one another and use low-voltage, differential signaling (LVDS). The first set of signals are adapted to be received on fewer lines and at a faster data rate than possible with an Integrated Disc Electronics (IDE) bus. In contrast, the second set of signals are serial to another and use TTL voltage levels and single-ended signaling. Additionally, the second set of signals use a packet format to represent a packet. The depacketizing circuit disassembles the packet represented by the second set of signals to generate a third set of signals, which are parallel to one another and use TTL, single-ended signaling.

Abstract: A transmission interface compatible with the AT Attachment Packet Interface (ATAPI) that achieves transfer rates greater than those possible with an Integrated Disc Electronics (IDE) bus. The transmission interface includes a transmission ATAPI circuit, a packetizing circuit and a converter. The transmission ATAPI circuit monitors the content of the ATAPI and, when a change is detected, generates a first set of signals representative of that change. The first set of signals are single-ended, parallel to one another and use Transistor-Transistor Logic (TTL) voltage levels. The packetizing circuit packetizes the first set of signals to generate a second set of signals, which representing a packet. The packet payload represents the change in the contents of the ATAPI. The second set of signals are also single-ended, parallel to one another and use TTL voltage levels. The converter converts the second set of signals into a third set of signals and couples these to a serial bus.

Abstract: An apparatus and method for interfacing integrated circuits having incompatible input-output signal offset voltages that is relatively inexpensive and yet is also insensitive to noise.