Abstract: In a digital convergence circuit within a video display system, an interpolation circuit for multiplying first and second predetermined correction values corresponding to a pair of sample points by a plurality of respective first and second weighting coefficient values corresponding to successive additional sample points (i) intermediate the first and second sample points. Circuitry is provided for detecting the number (N) of successive additional sample points (i) and in response generating a first address signal representative thereof. Further circuitry is provided for generating successive count address signals corresponding to the successive additional sample points (i). A memory is included for receiving the first and successive count address signals and in response generating respective ones of the first weighting coefficient values .alpha. in accordance with the relation .alpha.=i/N.